View SC28L202A1D_1305675.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
SC28L202 Dual universal asynchronous receiver/transmitter (DUART)
Objective specification Supersedes data of 2000 Jan 31 IC19 Data Handbook 2000 Feb 10
Philips Semiconductors
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL) (PRELIMINARY 2/10/00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OVERALL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRIEF DESCRIPTION OF FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitters and Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Character and Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Modes and Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DETAILED DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbitrating Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROGRAMMING THE HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER DESCRIPTION AND PROGRAMMING NOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers that control Global Properties of the 28L202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCCR - Global Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCCR(7:6) DACKN Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCCR(5:3): Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCCR(2:1): Interrupt vector configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCCR(0): Interrupt Status Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFSR A and B Special Feature & Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFSR(7:4) Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFSR(3) Status of loop back error check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SFSR(0) Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRR Test and Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRR(7) Test 2 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRR [6:0] - Chip Revision Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STCR - Scan Test Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SES - System Enable Status Register, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EOS - Enhanced Operation Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . These registers are generally concerned with formatting, transmitting and receiving data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR0 - Mode Register 0, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR0[7] Fixed length Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR0[5:4] - Tx interrupt fill level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR0[3] - FIFO Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR0[2:0] - Legacy Baud Rate Group Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1 - Mode Register 1, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1[7] - Receiver Request to Send (hardware flow control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1[6] - Receiver interrupt control bit 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1 [5] - Error Mode Select and sub modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1[4:3] - Parity Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1[2] - Parity Type Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1[1:0] - Bits per Character Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2 - Mode Register 2, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2[7:6] - Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2[7:6] = b'00 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2[7:6] = b'01 Automatic Echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2[7:6] = b'10 selects local loop back diagnostic mode. In this mode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2 [7:6] = b'11 Selects the Remote Loop back diagnostic mode. In this mode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2[5] Transmitter Request to Send Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2[4] - Clear to Send Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2[3:0] - Stop Bit Length Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 1 2 3 4 7 7 7 7 7 7 7 7 8 8 8 8 8 9 10 11 14 19 20 20 20 20 20 20 20 20 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 24
2000 Feb 10
i
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
MR3 - Mode Register 3, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR3[7 & 6] Xon/Xoff Character Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR3[5:4] Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR3[3:2] Xon/Xoff Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR3[1:0] Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RxCSR - Receiver Clock Select Register A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TxCSR Transmitter Clock Select Register A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rx and Tx Clock Select Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRx - Command Register Extension, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CR[7] - Lock Tx and Rx enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITES TO THE LOWER 5 BITS OF THE CR WOULD USUALLY HAVE CR[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CR[6] - Enable Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CR[5] - Enable Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CR[4:0] - Miscellaneous Commands (See Table below) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMAND REGISTER EXTENSION TABLE A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR - Channel Status Register A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR[7] - Received Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR[6] - Framing Error (FE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR[5] - Parity Error (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR[4] - Overrun Error (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR [3] - Transmitter Idle (Tx Idle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR[2] - Transmitter Ready (TxRDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR[1] - RxFIFO Full (RxFULL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR[0] - Receiver Ready (RxRDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR - Interrupt Status Register A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[7] - Input Change of State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[6] Fixed Watchdog Time-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[5] - Address Recognition Status Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[4] - Xon/Xoff Status Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[3] - Counter Timer Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[2] - Change in Channel Break Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[1] - RxINT. (Also Rx DMA hand shake at I/O pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[0] - TxINT. (Also Tx DMA hand shake at I/O pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR - Interrupt Mask Register A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR[7] COS enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR[6] Fixed Watchdog Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR[5] Address recognition enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR[4] Xon/Xoff Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR[3] Counter/Timer Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR[1] Receiver (Rx) Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR[0] Transmitter (Tx) Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RxFIFO - Receiver FIFO, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TxFIFO - Transmitter FIFO, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RxFIL - Receiver FIFO Interrupt Level, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RxFL - Receiver FIFO Fill Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TxFIL - Transmitter FIFO Interrupt Level A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TxEL - Transmitter FIFO Empty Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers for Character Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XonCR - Xon/Xoff Character Register A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XoffCR - Xoff Character Register A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARCR - Address Recognition Character Register A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XISR - Xon-Xoff Interrupt Status Register A and B (Reading this register clears XISR(7:4)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XISR[7:6] Received X Character Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XISR[5:4] Automatic transmission Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XISR[3:2] TxD Condition of the automatic flow control status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XISR[1:0] TxD X character Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WCXER Watch Dog, Character, Address and X Enable Register - A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Counters, Timers and Baud Rate generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PBRGPU - Programmable BRG Timer Reload Registers, Upper 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PBRGPL - Programmable BRG Timer Reload Registers, Lower 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTCS 0 and 1 - Counter Timer clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTVU - Counter Timer Value Registers, Upper 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTVL - Counter timer Value Registers, Lower 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PBRGCS - Programmable BRG Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTPU Counter Timer Preset Upper 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTPL Counter -Timer Preset Low 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 25 25 25 25 26 26 26 27 27 27 27 27 27 28 29 29 29 29 29 29 29 29 29 30 30 30 30 30 30 30 30 30 31 31 31 31 31 31 31 31 31 31 31 31 32 32 32 32 32 32 33 33 33 33 33 33 34 34 34 34 34 34 34 35 35
2000 Feb 10
ii
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
Registers of the Arbitrating Interrupt System and Bidding control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICR - Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCIR - Update CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIR - Current Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IVR - Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modification of the IVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GICR - Global Interrupting Channel Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GIBCR - Global Interrupting Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GITR - Global Interrupting Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GRxFIFO - Global RxFIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GTxFIFO - Global TxFIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCRBRK - Bidding Control Register - Break Change, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCRCOS - Bidding Control Register - Change of State, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCRx - Bidding Control Register - Xon/Xoff, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCRA - Bidding Control Register - Address, A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCR C/T - Bidding Control Register -C/T, 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCRLBE - Bidding Control Register - Received Loop Back Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers of the I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPCRL - Input Port Change Register Lower Nibble, A and B (n = A for A, n = B for B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPCRU - Input Port Change Register Upper Nibble, A and B (n = A for A, n = B for B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPR - Input Port Register, A and B (n = A for A, n = B for B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPCE - Input Change Detect Enable, A and B (n = A for A, n = B for B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/OPCR 0 - I/O Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/OPCR 1 - I/O Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/OPCR 2 - I/O Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/OPCR 3 - I/O Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOPR A and SOPR B - Set the Output Port Bits (OPR A and OPR B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROPR A and ROPR B - Reset ROPR Output Port Bits (OPR A and OPR B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPR - Output Port Register, A and B (n = A for A, n = B for B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THE REGISTERS FOR COMPATIBILITY WITH PREVIOUS DUARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER DESCRIPTIONS Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1 Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1 A[7] - Channel A Receiver Request-to-Send Control (Flow Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1[6] - Receiver interrupt control bit 1. See description under MR0[6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1 A[5] - Channel A Error Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1 A[4:3| - Channel A Parity Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1 A[2] - Channel A Parity Type Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR1 A[1:0] - Channel A Bits Per Character Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MR2 Mode Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR A[7] - Received Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR A[6] - Channel A Framing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR A[5] - Channel A Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR A[4] - Channel A Overrun Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR A[3] - Channel A Transmitter Empty (TxEMT A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR A[2] - Channel A Transmitter Ready (TxRDY A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR A[1] - Channel A FIFO Full (FFULL A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR A[0] - Channel A Receiver Ready (RxRDY A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR B - Channel B Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSR A - Channel A Clock Select Register CSR A [7:4] - Channel A Receiver Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSR Clock Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSR A [3:0] - Channel A EXTERNAL Transmitter Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSR B [7:4] - Channel B Receiver Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSR B [3:0] - Channel B Transmitter Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rx FIFO Register. For characters shorter than 8 bits the unused bits are set to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tx FIFO register. For characters shorter than 8 bits the unused bits are set to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CR A and B Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CR Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMAND REGISTER TABLE A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPCR Input Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPCR [7:4] I/03A, I/O2 A, I/O1 A, I/O0 A Change-of-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPCR [3:0] I/O3 A, I/O2 A, I/O1 A, I/O0 A logical level of I/O pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACR Auxiliary Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACR[7] - Baud Rate Generator Set Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACR[6:4] - Counter/Timer Mode And Clock Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACR [3:0] - I/O3 A, I/O2 A, I/O1 A, I/O0 A Change-of-State Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36 36 36 36 36 37 37 37 37 37 37 37 37 38 38 38 38 38 38 38 38 38 39 39 39 39 39 40 40 40 42 43 43 43 43 43 43 43 43 44 44 44 44 44 44 44 44 44 44 45 45 45 45 45 45 45 45 46 46 47 47 47 47 47 47 47
2000 Feb 10
iii
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
ISR - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[7] - Input Port Change Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[6] - Channel B Change In Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[5] - Rx B Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[4] - Tx B Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[3] - Counter Ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[2] - Channel A Change in Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[1] - Rx A Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR[0] - Tx A Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR - Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTPU Counter Timer Preset Upper (Counter/Timer 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTPL Counter -Timer Preset Lower (Counter/Timer 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTVU Counter Timer Value Upper (Counter/Timer 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTVL Counter -Timer Value Lower (Counter/Timer 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IVR Interrupt Vector register in 68K mode and General purpose read write register in the x86 mode . . . . . . . . . . . . . . . . . . . . . . . . . IPR Input Port Register I/O(6:0) A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPCR Output Port Configuration Register. Controls [7:2] B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOPR - Set Bits in the OPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROPR - Reset Bits in the OPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPR Output Port Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER MAP DETAIL (based on 28L92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER MAP (BASED ON 28L92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER MAP (BASED ON 28L92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER MAP (BASED ON 28L92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC ELECTRICAL CHARACTERISTICS123 (NOMINAL 5 VOLTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC CHARACTERISTICS1,2,3 (NOMINAL 5 VOLTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC ELECTRICAL CHARACTERISTICS1,2,3 (NOMINAL 3.3 VOLTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC CHARACTERISTICS1,2,3 (NOMINAL 3.3 VOLTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48 48 48 48 48 48 48 48 48 48 48 48 48 49 49 49 49 50 50 50 51 51 51 52 53 54 55 56 57 59 60
2000 Feb 10
iv
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
LIST OF FIGURES
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Reset Timing (80XXX mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Timing (80XXX mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing (68XXX mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Timing (Read Cycle) (68XXX mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Timing (Write Cycle) (68XXX mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Cycle Timing (68XXX mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Timing (80xxx mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter External Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Conditions on Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 61 62 62 63 63 64 64 65 65 65 66 66 67
LIST OF TABLES
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Interrupt Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC28L202 REGISTER BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver FIFO Interrupt Fill Level MR0(3)=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver FIFO Interrupt Fill Level MR0(3)=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter FIFO Interrupt Fill Level MR0(3)=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter FIFO Interrupt Fill Level MR0(3)=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver FIFO Interrupt Fill Level MR0(3)=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver FIFO Interrupt Fill Level MR0(3)=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter FIFO Interrupt Fill Level MR0(3)=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter FIFO Interrupt Fill Level MR0(3)=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate (Base on a 14.7456 MHz crystal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACR 6:4 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 20 22 22 22 22 40 41 42 42 42 42 45 47
2000 Feb 10
v
Philips Semiconductors
Objective specification
Dual UART
SC28L202
DESCRIPTION
The 28L202 is a high performance dual UART. Its functional and programming features closely match but greatly extend those of previous Philips dual channel UARTs. Its configuration on power up is similar that of the SC26C92. Its differences from the SC26C92 are: 256-character receiver, 256 character transmit FIFOs, 3 and 5 volt compatibility, 8 I/O ports for each UART - 16 total, arbitrating interrupt system and overall faster buss and data speeds. It is fabricated in an advanced 0.5 micron CMOS process that allows stand by current of less that 10 microamperes. It is a member of the IMPACT(R) line of Data Communications parts
* Three character recognition system per channel, used as:
- General purpose character recognition - Xon/Xoff character recognition - Address recognition Wake up (multi-drop or "9 bit") mode - System provides 4 levels of automation on a recognition event
* Programmable data format
- 5 to 8 data bits plus parity and 9 bit mode - Odd, even, no parity or force parity - 9/16,1, 1.5 or 2 stop bits
Pin or register programming will allow the device to operate with either the Motorola or Intel bus interface by changing the function of some pins (reset is inverted, DACKN, and IACKN enabled for example). The Philips Semiconductors 28L202 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system. The use of the Interrupt system provides intelligent interrupt vectors. The operating mode and data format of each channel may be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of twenty-seven fixed baud rates; a 16X clock derived from one of two programmable counter/timers, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems and bridges. Each receiver and transmitter is buffered by 256 character FIFOs to nearly eliminate the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability (Xon/Xoff and RTS/CTS) is provided to disable a remote transmitter when the receiver buffer is full. Also provided on the 28L202 is a multipurpose 8-bit I/O for each channel. These can be used as general-purpose I/O ports or can be assigned specific functions (such as clock inputs or status and interrupt outputs) under program control. Normally they will be used for modem control and DMA interface. All ports have change of state detectors and input sections are always active making output signals available to the internal circuits and the control processor. The 28L202 are available in 52-pin plastic quad flat pack (PQFP), or 56-pin TSSOP packages.
* 16-bit programmable Counter/Timer * Programmable baud rate for each receiver and transmitter
selectable from: - 27 fixed rates: 50 to 2.0 Meg baud (includes MIDDI(R) rate) - Other baud rates via external clocks and C/T - Programmable user-defined rates derived from a programmable Counter/timer - External 1X or 16X clock
* Parity, framing, and overrun error detection * False start bit detection * Line break detection and generation * Programmable channel mode
- Normal (full-duplex) - Automatic echo - Local loop back - Remote loop back - Multi-drop mode (also called `wake-up' or `9-bit')
* Multi-function 8 bit I/O input port per channel loosely assigned to
each channel. - Can serve as clock or control inputs - Change of state detection on eight inputs - Inputs have typically >100Mohm pull-up resistors - Modem and DMA interface
* Versatile arbitrating interrupt system
- Interrupt system totally supports `single query' polling - Output port can be configured to provide a total of up to six separate interrupt type outputs that may be wire ORed (switched to open drain). - Each FIFO can be independently programmed for any of 256 interrupt levels - Watch dog timer for each receiver
FEATURES
* Member of IMPACT family: 3.3 to 5.0 volt , -40C to +85C and
68K for 80xxx bus interface for all devices.
* Dual full-duplex independent asynchronous receiver/transmitters * 256 character FIFOs for each receiver and transmitter * Powers up to 9600 baud, 1 stop bit, no parity, 1 stop bit, interrupt
disabled, all I/O set to input.
* Pin programming to 68K or 80xxx bus interface
2000 Feb 10 1
* Maximum data transfer rates: 1X - 3 Mb/sec, 16X - 2 Mb/sec * Automatic wake-up mode for multi-drop applications * Start-end break interrupt/status * Detects break which originates in the middle of a character * On-chip crystal oscillator * Power down mode at less than 10 a * Receiver time-out mode * Single +3.3V or +5V power supply
Philips Semiconductors
Objective specification
Dual UART
SC28L202
ORDERING INFORMATION
Industrial D i ti Description (Preliminary as of 1/31/00) 52-Pin Plastic Quad Flat Pack (PQFP) 56-pin TSSOP VCC = +3.3 +5V 10%, Tamb = -40C to +85C SC28L202A1B SC28L202A1D SOT379-1 SOT364-1 D i Drawing Number
2000 Feb 10
2
Philips Semiconductors
Objective specification
Dual UART
SC28L202
PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL) (PRELIMINARY 2/10/00)
Symbol I/M D0-D7 CEN Pin type I I/O I Name and Function Bus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table. Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A6-A0 inputs. When High, places the D0-D7 lines in the 3-State condition. Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN. Address Inputs: Select the DUART internal registers and ports for read/write operations. Reset: A High level clears internal registers (SR A, SR B, IMR, ISR, OPR, OPCR), places I/O[7:0] A and B at high impedance input state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxD A and TxD B outputs in the mark (High) state. Sets MR pointer to MR1 9600 baud, 1 start, no parity and 1 stop bit(s). (See Reset table) Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eighteen (18) maskable interrupting conditions are true. Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 9). Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 9). If X1/Sclk is driven from an external source, this pin must be open or not driving more that 2 CMOS or TTL loads. Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High; "space" is Low. Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is High; "space" is Low. Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle or when operating in local loop back mode. "Mark" is High; "space" is Low. Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `Mark' is High; `space' is Low. General-purpose input and output ports channel A: The character of these pins is controlled by I/OPCR. They may be inputs or outputs and will present many internal clocks and interrupt signals: RTS, CTS, DTR, DSR etc. All have change of state detectors and the input is always active. These pins are set to input only when addressed from the low order 16 address space. When these pins are configured for interrupt type signals (RxRDY, TxRDY, C/TRDY) They switch to open drain outputs. General-purpose input and output ports channel B: The character of these pins is controlled by I/OPCR. They may be inputs or outputs and will present many internal clocks and interrupt signals: RTS, CTS, DTR, DSR etc. All have change of state detectors and the input is always active. These pins are set to output only when addressed from the low order 16 address space. When these pins are configured for interrupt type signals (RxRDY, TxRDY, C/TRDY) They switch to open drain outputs. Power Supply: +3.3 or +5V supply input 10% (4 pins). Operation is assured from 2.97 to 5.5 volts. Timing parameters are specified with respect to the Vcc being at 3.3 of 5.0 volts +/- 10% Ground (5 pins)
WRN RDN A6-A0 RESET
I I I I
IRQN X1 / Sclk X2
O I O
RxD A RxD B TxD A
I I O
TxD B
O
I/O[7:0]A
I/O
I/O[7:0}B
I/O
Vcc GND
Power Power
2000 Feb 10
3
Philips Semiconductors
Objective specification
Dual UART
SC28L202
CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA)
Symbol I/M D0-D7 CSN R/WN IACKN DACKN A6-A0 RESETN Pin type I I/O I I I O I I Name and Function Bus Configuration: When low configures the bus interface to the Conditions shown in this table. Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the R/WN and A0-A6 inputs. When High, places the D0-D7 lines in the 3-State condition. Read/Write: Input Signal. When CSN is low R/WN high input a read cycle, when low a write cycle. Interrupt Acknowledge: Active low input indicates an interrupt acknowledge cycle. Usually asserted by the CPU in response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN. Data Transfer Acknowledge: A 3-State active -low output asserted in a write, read, or interrupt acknowledge cycle to indicate proper transfer of data between the CPU and the DUART. Address Inputs: Select the DUART internal registers and ports for read/write operations. Reset: A low level clears internal registers (SR A , SR B, IMR, ISR, OPR, OPCR), places I/O[7:0] A and B at high impedance input state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxD A and TxD B outputs in the mark (High) state. Sets MR pointer to MR1, 9600 baud, 1 start, no parity and 1 stop bit(s). (See Reset Table) Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eighteen (18) maskable interrupting conditions are true. Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 9). Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin to ground (see Figure 9). If Sclk is driven from an external source, this pin must be left open. Channel A Receiver Serial Data Input: The least significant bit is received first. "Mark" is High; "space" is Low. Channel B Receiver Serial Data Input: The least significant bit is received first. "Mark" is High; "space" is Low. Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the "mark" condition when the transmitter is disabled, idle or when operating in local loop back mode. "Mark" is High; "space" is Low. Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `Mark' is High; `space' is Low. General-purpose input and output ports channel A: The character of these pins is controlled by I/OPCR. They may be inputs or outputs and will present many internal clocks and interrupt signals: RTS, CTS, DTR, DSR etc. All have change of state detectors and the input is always active. These pins are set to input only when addressed from the low order 16 address space. When these pins are configured for interrupt type signals (RxRDY, TxRDY, C/TRDY) They switch to open drain outputs. General-purpose input and output ports channel B: The character of these pins is controlled by I/OPCR. They may be inputs or outputs and will present many internal clocks and interrupt signals: RTS, CTS, DTR, DSR etc. All have change of state detectors and the input is always active. These pins are set to output only when addressed from the low order 16 address space. When these pins are configured for interrupt type signals (RxRDY, TxRDY, C/TRDY) They switch to open drain outputs Power Supply: +3.3 or +5V supply input 10% (4 Vcc Pins) ). Operation is assured from 2.97 to 5.5 volts. Timing parameters are specified with respect to the Vcc being at 3.3 of 5.0 volts +/- 10% Ground (5 Vss Pins)
IRQN X1 / Sclk X2 RxD A RxD B TxD A
O I O I I O
TxD B
O
I/O[7:0]A
I/O
I/O[7:0}B
I/O
Vcc Vss
Power Power
2000 Feb 10
4
Philips Semiconductors
Objective specification
Dual UART
SC28L202
28L202 Pin Configurations
80xxx 56 Pin TSSOP
Pin Function Pin Function Pin
68xxx 56 Pin TSSOP
Function Pin Function
1 Vcc 2 Vss 3 A6 4 A5 5 A4 6 A3 7 RxDA 8 RESET 9 D7 10 D6 11 D5 12 D4 13 Vcc 14 NC 15 Vss 16 Vss 17 D3 18 D2 19 D1 20 D0 21 I/M 22 RxDB 23 A2 24 A1 25 A0 26 (IACKN) 27 Vcc 28 Vss
29 CEN 30 WRN 31 RDN 32 TxDB 33 I/O7B 34 I/O6B 35 I/O5B 36 I/O4B 37 I/O3B 38 I/O2B 39 I/O1B 40 I/O0B 41 Vcc 42 Vcc 43 Vss 44 Vss 45 I/O7A 46 I/O6A 47 I/O5A 48 I/O4A 49 I/O3A 50 I/O2A 51 I/O1A 52 I/O0A 53 TxDA 54 IRQN 55 X1 / SCLK 56 X2
1 Vcc 29 CEN 2 Vss 30 RWN 3 A6 31 DACKN 4 A5 32 TxDB 5 A4 33 I/O7B 6 A3 34 I/O6B 7 RxDA 35 I/O5B 8 RESETN 36 I/O4B 9 D7 37 I/O3B 10 D6 38 I/O2B 11 D5 39 I/O1B 12 D4 40 I/O0B 13 Vcc 41 Vcc 14 NC 42 Vcc 15 Vss 43 Vss 16 Vss 44 Vss 17 D3 45 I/O7A 18 D2 46 I/O6A 19 D1 47 I/O5A 20 D0 48 I/O4A 21 I/M 49 I/O3A 22 RxDB 50 I/O2A 23 A2 51 I/O1A 24 A1 52 I/O0A 25 A0 53 TxDA 26 IACKN 54 IRQN 27 Vcc 55 X1 / SCLK 28 Vss 56 X2
SD00691
2000 Feb 10
5
Philips Semiconductors
Objective specification
Dual UART
SC28L202
28L202 Pin Configuration
52
51
50
49
48
47
46
45
44
43
42
41
40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
39 38 37 36 35
52 Pin PQFP
34 33 32 31 30 29 28 27
80xxx 52 Pin PQFP Pin Function Pin Function 1 RxDA 27 I/O5B 2 RESET 28 I/O4B 3 D7 29 I/O3B 4 D6 30 I/O2B 5 D5 31 I/O1B 6 D4 32 I/O0B 7 Vcc 33 Vcc 8 Vss 34 Vss 9 D3 35 I/O7A 10 D2 36 I/O6A 11 D1 37 I/O5A 12 D0 38 I/O4A 13 I/M 39 I/O3A 14 RxDB 40 I/O2A 15 A2 41 I/O1A 16 A1 42 I/O0A 17 A0 43 TxDA 18 (IACKN) 44 IRQN 19 Vcc 45 X1 / SCLK 20 Vss 46 X2 21 CEN 47 Vcc 22 WRN 48 Vss 23 RDN 49 A6 24 TxDB 50 A5 25 I/O7B 51 A4 26 I/O6B 52 A3
68xxx 52 Pin PQFP Pin Function Pin Function 1 RxDA 27 I/O5B 2 RESETN 28 I/O4B 3 D7 29 I/O3B 4 D6 30 I/O2B 5 D5 31 I/O1B 6 D4 32 I/O0B 7 Vcc 33 Vcc 8 Vss 34 Vss 9 D3 35 I/O7A 10 D2 36 I/O6A 11 D1 37 I/O5A 12 D0 38 I/O4A 13 I/M 39 I/O3A 14 RxDB 40 I/O2A 15 A2 41 I/O1A 16 A1 42 I/O0A 17 A0 43 TxDA 18 IACKN 44 IRQN 19 Vcc 45 X1 / SCLK 20 Vss 46 X2 21 CEN 47 Vcc 22 RWN 48 Vss 23 DACKN 49 A6 24 TxDB 50 A5 25 I/O7B 51 A4 26 I/O6B 52 A3
SD00692
2000 Feb 10
6
Philips Semiconductors
Objective specification
Dual UART
SC28L202
OVERALL DESCRIPTION
The SC28L202 is composed of several functional blocks. They are listed in the approximate order of hierarchy as seen from the pins of the device.
has 8 programmable clock sources derived from internal and external signals. I/O ports The SC28L202 is provided with 16 I/O ports. These ports are true input and/or output structures and are equipped with a change of state detector. The input circuit of these pins is always active. Under program control the ports my display internal signals or static logic levels. The functions represented by the I/O ports include hardware flow control. Modem signals, signals for interrupt conditions or various internal clocks and timing intervals. Noisy inputs to the I/O ports are filtered (de-bounced) by a 38.4 KHz clock. Change of state detectors are provided for each pin and are always available. UARTs The UARTs are fully independent, full duplex and provide all normal asynchronous functions: 5 to 8 data bits, parity odd or even, programmable stop bit length, false start bit detection. Also provided are 256 byte FIFOs Xon/Xoff software flow. The BRG, Counter-timer, or external clocks provide the baud rates. The receivers and transmitters may operate in either the "1x" or "16x" modes. The control section recognizes two address schemes. One is the subset of the other: a four (4) bit and an eight (7) bit address spaces. The purpose of this is to provide a large degree of software compatibility with previous Philips/Signetics UARTs. Transmitters and Receivers The transmitters and receivers are independent devices capable of full duplex operation. Baud rates, interrupt and status conditions are under separate control. Transmitters have automatic simplex "turnaround". Receivers have RTS and Xon/Xoff flow control and a three character recognition system. FIFO Structures The FIFO structure is 256 bytes for each of the four FIFOs in the DUART. They are organized as 11 bit words for the receiver and 8 bye words for the transmitter. The interrupt level may be set at any value from 0 to 255. The interrupt level is independently set for each FIFO. FIFO interrupt and DMA fill/empty levels are controlled by the RxFIL and TxFIL registers which may set any level of the from 0 to 255. The signals associated with the FIFO fill levels are available to the I/O pins (for interrupt or DMA) and to the arbitrating interrupt system for "fine tuning" of the arbitration authority. Intelligent Interrupt Arbitration The interrupt system uses a highly programmable arbitrating technique to establish when an interrupt should be presented to the processor. The advantageous feature of this system is the presentation of the context of the interrupt. It is presented in both a current interrupt register and in the interrupt vector. The context of the interrupt shows the interrupting channel, identifies which of the 18 possible sources in requesting interrupt service and in the case of a receiver or transmitter gives the current fill level of the FIFO. The content of the current interrupt register also drives the Global Registers of the interrupt system. These registers are indirect addresses (pointers) to the interrupt source requesting service. Programming of Bid Control Registers allows the interrupt level of any source to be varied at any time over a range of 256 levels. Character and Address Recognition The character recognition system is designed as a general-purpose system. There is one for each UART. Each recognition block stores
* Bus interface. 68K or x86 format * Timing Circuits * I/O Ports * UARTs * Transmitters and Receivers * FIFO Structures * Arbitrating Interrupt Structure * Character & Address Recognition * Flow Control * Test and Software compatibility with previous Philips (Signetics)
UARTs
BRIEF DESCRIPTION OF FUNCTIONAL BLOCKS
Bus Interface The Two basic modes of Bus Interface The bus interface operates in "68K" or "x86" format as selected by the I/M pin. The signals used by this section are the Address, Data bus, Chip select, read/write, Data acknowledge and Interrupt acknowledge and Interrupt request. Assertion of DACKN requires two edges of the Sclk after the assertion of CEN. The default mode is the x86 mode. Pin or register programming may change it to he 68K mode Timing Circuits Crystal Oscillator The crystal oscillator is the main timing element for the 28L202. It is nominally set at 14.7456 MHz. Operation with a crystal as a frequency standard is specified from 7 MHz to 16.2 MHz The use of an external clock allows all frequencies to 50 MHz. Clock prescalers are provided to match various available system clocks to those needed for baud rate generation. NOTE: if an external clock is used X2 should not drive more than 2 CMOS or 2 TTL equivalents. Fixed Rate BRG The BRG is the baud rate generator, is driven by the X1/Sclk input through a programmable prescale divider. It generates all of the 27 "fixed" internal baud rates. This baud rate generator is designed to generate the industry standard baud rates from a 14.7456 MHz crystal or clock frequency. X1/Sclk frequencies different from 14.7456 MHz will cause the "fixed" baud rates to change by exactly the ratio of 14.7456 to the different frequency. Counter-Timer The two counter-timers are programmable 16 bit "down" counters. It provides miscellaneous baud rates, timing periods and acts as an extra watchdog timer for the receivers. It has 8 programmable clock sources derived from internal and external signals. It may also act as a character counter for the receiver. Interrupts from the counter timer are generated as it passes through zero. Programmable BRG (PBRG) This is another 16 bit programmable counter to generate only baud rates or miscellaneous clock frequencies. Its output is available to the receivers and transmitters and may be delivered to I/O ports. It
2000 Feb 10
7
Philips Semiconductors
Objective specification
Dual UART
SC28L202
up to three characters. The recognition is done on a byte boundary and sets status and interrupt when recognition events occur. Three modes of automatic operation are provided for the in-band flow control and three modes of automatic operation are provided for address recognition. Both in-band flow control and address recognition may also be completely under the control of the host processor. A subset of the recognition system is Xon/Xoff character recognition and the recognition of the multi-drop address character. If Xon/Xoff or multi-dorp function is enabled the recognition system passes the information about the recognition event to the appropriate receiver or transmitter state machine for execution. In any case the information about a recognition event is available to the interrupt system and to the control processor. Flow Control Flow control is implemented in either the traditional RTS/CTS protocol or in the "inbound" Xon/Xoff method. Both may be controlled by fully/partially automatic methods or by interrupt generation. Test Modes and Software Four test modes are provided to verify UART function and processor interface integrity. The first three are Auto echo, Local Loop Back, and Remote Loop Back. Through local loop back the software developer may verify all of the interrupt, flow control; the hardware designer verify all of the timing and pin connections. This information is obtained without any recourse to external test equipment, logic analyzers or terminals. The fourth, Receiver Error Loop back verification, employs a method of automatic checking (accounting for transmission delays) of the transmitted data to as echoed back through the remote receiver. Errors generate interrupt and status events.
high and immediately returns to the high impedance state. This will occur at the termination of the CEN or IACKN cycle. NOTE: The faster X86 timing may be used in the 68K mode IF the bus cycles are faster than 1/2 period of the Sclk clock. Withdrawing CEN before DACKN prevents the generation of DACKN. In this case bus timing is effectively that of the X86 mode. When operating in the "x86" mode DACKN is not generated. Data is written on the termination of CEN or WRN whichever one occurs first. Read data is presented from the leading edge of the read condition (CEN and RDN both low). IACKN Cycle, Update CIR When the host CPU responds to the interrupt, it will usually assert the IACKN signal low. This will cause the intelligent interrupt system of the DUART to generate an IACKN cycle in which the condition of the interrupting source is determined. When IACKN asserts, the last valid of the interrupt arbitration cycle is captured in the CIR. The value captured presents all of the important details of the highest priority interrupt at the moment the IACKN (or the "Update CIR" command) was asserted. Due to system interrupt latency the interrupt condition captured by the CIR may not be the condition that caused the initial assertion of the interrupt. The Dual UART will respond to the IACKN cycle with an interrupt vector. The interrupt vector may be a fixed value, the content of the Interrupt Vector Register, or when "Interrupt Vector Modification" is enabled via ICR, it may contain codes for the interrupt type and/or interrupting channel. This allows the interrupt vector to steer the interrupt service directly to the proper service routine. The interrupt value captured in the CIR remains until another IACKN or "Update CIR" command is given to the DUART. The interrupting channel and interrupt type fields of the CIR set the current "interrupt context" of the DUART. The channel component of the interrupt context allows the use of Global Interrupt Information registers that appear at fixed positions in the register address map. For example, a read of the Global RxFIFO will read the channel B RxFIFO if the CIR interrupt context is channel B receiver. At another time read of the GRxFIFO may read the channel A RxFIFO (CIR holds a channel A receiver interrupt) and so on. Global registers exist to facilitate qualifying the interrupt parameters and for writing to and reading from FIFOs without explicitly addressing them. The CIR will load with 0x00 if IACKN or Update CIR is asserted when the arbitration circuit is NOT asserting an interrupt. In this condition there is no arbitration value that exceeds the threshold value. When Interrupt vector modification is active in this situation the interrupt vector bits associated with the CIR will all be zero. A zero type field indicates nothing with in the DUART is requiring processor service. NOTE: IACKN is essentially a special read action where the value of the interrupt vector is presented to the data bus. Timing Circuit Crystal Oscillator The crystal oscillator operates directly from a crystal, tuned between 7.0 MHz and 16.2 MHz connected across the X1/Sclk and X2 inputs with a minimum of external components. BRG values listed for the clock select registers correspond to a 14.7456 MHz crystal frequency. Use of different frequencies will change the "standard" baud rates by precisely the ratio of 14.7456 MHz to the different crystal frequency. An external clock up to 50 MHz frequency range may be connected to X1/Sclk pin. If an external clock is used instead of a crystal, X1/Sclk must be driven and X2 left floating or driving a load of not
DETAILED DESCRIPTIONS
NOTE: For the convenience of the reader some paragraphs of the following sections are repeated in descriptions of closely linked functions described in other sections. Bus Interface The bus interface operates in two modes selected by the I/M pin. If this pin is high or left open the signals DACKN signal is not generated or used and data flow to and from the chip is controlled by the state the CEN, RDN, WRN pin combination. If the I/M pin is tied low the data is written to the device when the DACKN pin is asserted low by the DUART. Read data is presented by a delay from CEN active. The Host interface is comprised of the signal pins CEN, WRN RDN, (or R/WN) IACKN, DACKN, IRQN, 6 address pins and 8 three-state data bus pins. Addressing of the various functions of the DUART is through the address bus A(6:0). Data is presented on the 8-bit data bus. DACKN Cycle When operating in the "68K" mode bus cycle completion is indicated by the DACKN pin (an open drain signal) going low. The timing of DACKN is by GCCR(6) where two time delays area available. The delay begins with the falling edge of CEN and DACKN is presented after either two edges of he X1/Sclk (1/2 X1/Sclk Cycle) or, under program control, a short internal delay of less than 50 ns. Usually in this mode the address and data are set up with respect to the leading edges of the bus cycle. The DACKN pin is a three state driver. At the termination of an access to the L202 a very short pulse (less than 5 ns) drives the pin 2000 Feb 10 8
Philips Semiconductors
Objective specification
Dual UART
SC28L202
more than 2 CMOS or TTL equivalents. The X1/Sclk clock serves as the basic timing reference for the baud rate generator (BRG) and is available to the programmable BRG (PBRG), counter-timers, control logic and the UART receivers and transmitters. Baud Rate Generator BRG The baud rate generator operates from the oscillator or external X1/Sclk clock input and generates 27 commonly used data communications baud rates (including MIDDI) ranging from 50 to 921.6K baud. These common rates may be increased (up to 3000K baud) when faster clocks are used on the X1/Sclk clock input. (See Receiver and Transmitter Clock Select Register descriptions.) All of these are available simultaneously for use by any receiver or transmitter. The clock outputs from the BRG are at 16X the actual baud rate. Please see counter timer description for a description of the frequency error that the asynchronous protocol may tolerate. Depending on character length it varies from 4.1% to 6.7%. Counter-Timer The two Counter/Timers are programmable 16 bit dividers that are used for generating miscellaneous clocks or generating timeout periods. These clocks may be used by any or all of the receivers and transmitters in the DUART or may be directed to an I/O pin for miscellaneous use. Counter/Timer programming The counter timer is a 16-bit programmable divider that operates in one of four modes: character count, counter, timer, and time out. Character count counts characters. The timer mode generates a square wave. In the counter mode it generates a time delay. In the time out mode it monitors the time between received characters. The C/T uses the numbers loaded into the Counter/Timer Lower Register (CTPL) and the Counter/Timer Upper Register (CTPU) as its divisor. The counter timer is controlled with six commands: Start/Stop C/T, Read/Write Counter/Timer lower register and Read/Write Counter/Timer upper register. These commands have slight differences depending on the mode of operation. Please see the detail of the commands under the CTPL/CTPU Register descriptions. Whenever the these timers are selected via the receiver or transmitter Clock Select register their output will be configured as a 16x clock for the respective receiver or transmitter. Therefore one needs to program the timers to generate a clock 16 times faster than the data rate. The formula for calculating 'n', the number loaded to the CTPU and CTPL registers, based on a particular input clock frequency is shown below. For the timer mode the formula is as follows: n+ Clockinputfrequency (2 16 (Baud rate desired))
of 1.14% or 1.12% respectively, well within the ability of the asynchronous mode of operation. Higher input frequency to the counter reduces the error effect of the fractional division One should be cautious about the assumed benign effects of small errors since the other receiver or transmitter with which one is communicating may also have a small error in the precise baud rate. In a "clean" communications environment using one start bit, eight data bits and one stop bit the total difference allowed between the transmitter and receiver frequency is approximately 4.6%. Less than eight data bits will increase this percentage. Programmable Baud Rate Generators. PBRG Two PBRG Counters (Used only for random baud rate generation) The two PBRG Timers are programmable 16 bit dividers that are used for generating miscellaneous clocks. These clocks may be used by any or all of the receivers and transmitters in the SC28L202 or output to the general purpose I/O pins. Each timer unit has eight different clock sources available to it as described in the PBRG clock source Register. Note that the timer run and stop controls are also contained in this register. The PBRG counters generate a symmetrical square wave whose half period is equal in time to the division of the selected PBRG Timer clock source by the number loaded to the PBRGPU and PBRGPL Preset Registers. Thus, the output frequency will be the clock source frequency divided by twice the 16 bit value loaded to these registers. This is the result of counting down once for the high portion of the output wave and once for the low portion. Whenever the these timers are selected via the receiver or transmitter Clock Select register their output will be configured as a 16x clock for the respective receiver or transmitter. Therefore one needs to program the timers to generate a clock 16 times faster than the data rate. The formula for calculating 'n', the number loaded to the PBRGPL and PBRGPU registers, is the same as shown above I/O Ports Eight I/O ports are "loosely" provided for each channel. They may be programmed to be inputs or outputs. The input circuits are always active whether programmed as and input or an output. In general a 2-bit code in the I/OPCR (I/O Port Control Register) controls what function these pins will present. All I/O ports default to high impedance input state on power up. When calling software written for previous Philips (Signetics) DUARTs the user should be sure to declare I/O ports to be inputs where drivers may be attached to an I/O port pin that previous software had expected to be an output. Input Characteristics of the I/O ports Eight I/O pins are provided for each channel. These pins are configured individually to be inputs or outputs. As inputs they may be used to bring external data to the bus, as clocks for internal functions or external control signals. Each I/O pin has a "Change of State" detector. The change detectors are used to signal a change in the signal level at the pin (Either 0 to 1 or 1 to 0 transitions). The level change on these pins must be stable for 25 to 50 us (two edges of the 38.4 KHz baud rate clock) before the detectors will signal a valid change. These are typically used for interface signals from modems to the DUART and from there to the host. Output Port of the I/O ports The OPR, I/OPCR, MR, and CR registers may control the I/O pins when configured as outputs. (For the control in the loser 16 position address space the control register is the OPCR) Via appropriate programming the pins of the output port may be configures as another parallel port to external circuits, or they may represent internal conditions of the UART. When this 8-bit port is used as a 9
NOTE: `n' may assume a value of 1. In previous Philips data communications controllers this value was not allowed. The Counter/Timer Clock Select Register (CTCS) controls the Counter/Timer input frequency. The frequency generated from the above formula will be at a rate 16 times faster than the desired baud rate. The transmitter and receiver state machines include divide by 16 circuits, which provide the final frequency and provide various timing edges used in the qualifying the serial data bit stream. Often this division will result in a non-integer value: 26.3 for example. One may only program integer numbers to a digital divider. There for 26 would be chosen. If 26.7 were the result of the division then 27 would be chosen. This gives a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error 2000 Feb 10
Philips Semiconductors
Objective specification
Dual UART
SC28L202
general-purpose output port, the output port pins drive inverse logic levels of the individual bits in the Output Port Register (OPR). The OPR register is set and reset by writing to the SOPR and ROPR addresses. (See the description of the SOPR and ROPR registers). The output pins will drive the same data polarity of the OPR registers. The I/OPCR (or the OPCR) register conditions these output pins to be controlled by the OPR or by other signals in the chip. Output ports are driven high on hardware reset.
UART Operation
Receiver and Transmitter The Dual UART has two full duplex asynchronous receiver/transmitters. The operating frequency for the receiver and transmitter can be selected independently from the baud rate generator, the counter, or from an external input. Registers that are central to basic full-duplex operation are the mode registers (MR0, MR1 and MR2), the clock select registers (RxCSR and TxCSR), the command register (CR), the status register (SR), the transmit holding register (TxFIFO), the receive holding register (RxFIFO), interrupt status register (ISR) and interrupt mask register (IMR). MR3 does not exist in 92 mode. MR3 is used in the control of the intelligent operations of the L202. Transmitter Status Bits The SR (Status Register, one per UART) contains two bits that show the condition of the transmitter FIFO. These bits are TxRDY and Tx Idle. TxRDY means the TxFIFO has space available for one or more bytes; Tx Idle means The TxFIFO is completely empty and the last stop bit has been completed - the transmitter is underrun. Tx Idle can not be active without TxRDY also being active. These two bits will go active upon initial enabling of the transmitter Transmission resumes and the Tx Idle bit is cleared when the CPU loads at least one new character into the TxFIFO. The TxRDY will not extinguish until the TxFIFO is completely full. The TxRDY bit will always be active when the transmitter is enabled and there is at lease one open position in the TxFIFO. The transmitter is disabled by a hardware reset, a transmitter reset in the command register or by the transmitter disable bit also in the command register (CR). The transmitter must be explicitly enabled via the CR before transmission can begin. Note that characters cannot be loaded into the TxFIFO while the transmitter is disabled, hence it is necessary to enable the transmitter and then load the TxFIFO. It is not possible to load the TxFIFO and then enable the transmission. Note the difference between transmitter disable and transmitter reset. Either hardware or software may cause the reset action. When reset the transmitter stops transmission immediately. The transmit data output will be driven high, transmitter status bits set to zero and any data remaining in the TxFIFO is effectively discarded. The transmitter disable is controlled by the Tx Enable bit in the command register. Setting this bit to zero will not stop the transmitter immediately but will allow it to complete any tasks presently underway. It is only when the last character in the TxFIFO and its stop bit(s) have been transmitted that the transmitter will go to its disabled state. While the transmitter enable/disable bit in the command register is at zero the TxFIFO will not accept any more characters and the Tx Idle and TxRDY bits of the status register set to zero.
Transmission of "break" Transmission of a break character is often needed as a synchronizing condition in a data stream. The "break" is defined as a start bit followed by all zero data bits by a zero parity bit (if parity is enabled) and a zero in the stop bit position. The forgoing is the minimum time to define a break. The transmitter can be forced to send a break (continuous low condition) by issuing a start break command via the CR. Once the break starts, the TxD output remains low until the host issues a command to "stop break" via the CR or the transmitter is issued a software or hardware reset. In normal operation the break is usually much longer than one character time. 1x and 16x modes, Transmitter The transmitter clocking has two modes: 16x and 1x. Data is always sent at the 1x rate. However the logic of the transmitter may be operated with a clock that is 16 times faster than the data rate or at the same rate as the data i.e. 1x. All clocks selected internally for the transmitter (and the receiver) will be 16x clocks. Only when an external clock is selected may the transmitter logic and state machine operate in the 1x mode. The 1x or 16x clocking makes little difference in transmitter operation. (This is not true in the receiver) In the 16X-clock mode the transmitter will recognize a byte in the TxFIFO within 1/16 to 2/16-bit time and thus begin transmission of the start bit. In the 1x mode this delay may be up to 2 bit times. Transmitter FIFO The FIFO configuration of the as 28L202 is 256 8-bit words. Interrupt levels may be set to any level within the FIFO size and may be set differently for each FIFO. Logic associated with the FIFO encodes the number of empty positions for presentation to the interrupt arbitration system. The encoding value is the number of empty positions. Thus, an empty TxFIFO will bid with the value or 255; when full it will not bid at all; one position empty bids with the value 0. A Full TxFIFO will not bid since no character is available. Normally TxFIFO will present a bid to the arbitration system whenever it has one or more empty positions. The Bits of the TxFIFO Interrupt Level in the MR0(5:4) allow the user to modify this characteristic so that bidding will not start until one of four levels (one or more filled, empty, 16 filled, 240 filled, full) have been reached. As will be shown later this feature may be used to make moderate improvements in the interrupt service efficiency. A similar system exists for the Receiver. Transmitter The 28L202 is conditioned to transmit data when the transmitter is enabled through the command register. The transmitter of the 28L202 indicates to the CPU that it is ready to accept a character by setting the ISR TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at I/O4 or IRQN. When the transmitter is initially enabled the TxRDY and Tx Idle bits will be set in the status register. When a character is loaded to the transmit FIFO the Tx Idle bit will be reset. The Tx Idle bit will not set until the transmit FIFO is empty and the transmit shift register has finished transmitting the stop bit of the last character written to the transmit FIFO. The TxRDY bit is set whenever the transmitter is enabled and the TxFIFO is not full. Data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. Characters cannot be loaded into the TxFIFO while the transmitter is disabled. The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD output pin. It automatically sends a start bit
2000 Feb 10
10
Philips Semiconductors
Objective specification
Dual UART
SC28L202
followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits, if a new character is not available in the TxFIFO, the TxD output remains High and the Tx Idle bit in the Status Register (SR) will be set to 1. Transmission resumes and the Tx Idle bit is cleared when the CPU loads a new character into the TxFIFO. If the transmitter is disabled, it continues operating until the character currently being transmitted is completely sent out. The transmitter can be forced to send a continuous Low condition by issuing a send break command. The transmitter can be reset through a software command. If it is reset, operation ceases immediately and the transmitter must be enabled through the command register before resuming operation. If CTS option of hardware flow control is enabled (MR2 [4] = 1), the CTS input at I/O0 or I/O1 must be Low in order for the character to be transmitted. The transmitter will check the state of the CTS input at the beginning of each character transmitted. If it is found to be High, the transmitter will delay the transmission of any following characters until the CTS has returned to the low state. CTS going high during the serialization of a character will not affect that character. It is an interesting point of the I/O system inputs being always active that by enabling transmitter to be sensitive the I/O0 or I/O1 and then controlling the I/O pin as an out put that one is able to control the transmitter flow via software control of the I/O pin. The transmitter can also control the RTSN outputs, I/O0 or I/O1 via MR2 [5]. When this mode of operation is set (often referred to as the RS-485 method) the meaning of the I/O0 B or I/O1 B signals is "all bytes loaded to the transmitter's FIFO have been transmitted including the last stop bit(s). See the MR2(5) description for enabling this automatic function. Receiver Operation Receiver The receiver accepts serial data on the RxD pin, converts the serial input to parallel format, checks for start bit, stop bit, parity bit (if any), framing error or break condition, and presents the assembled character and its status condition to the CPU via the RxFIFO. Three status bits are FIFOed with each character received. The RxFIFO is really 11 bits wide: eight data and 3 status. Unused FIFO bits for character lengths less than 8 bits are set to zero. It is important to note that in the asynchronous protocol the receiver logic considers the entire message to be contained within the start bit to the stop bit. It is not aware that a message may contain many characters. The receiver returns to its idle mode at the end of each stop bit! As described below it immediately begins to search for another start bit, which is normally, of course, immediately forthcoming. 1x and 16x mode, Receiver The receiver operates in one of two modes: 1x and 16x. Of the two, the 16x is more robust and the preferred mode. Although the 1x mode may allow a faster data rate is does not provide for the alignment of the receiver 1x data clock to that of the transmitter. This strongly implies that the 1x clock of the remote transmitter is available to the receiver; the two devices are physically close to each other. The 16x mode operates the receiver logic at a rate 16 times faster than the 1x data rate. This allows for validation of the start bit length, the validation of level changes at the receiver serial data input (RxD), and the validation of the stop bit length. Of most importance
in the 16x mode is the ability of the receiver logic to align the phase of the internally generated receiver 1x data clock to that of the received start bit of the remote transmitter. This occurs with an accuracy of less than 1/16 bit time. Receiver The receiver of the 28L202 is conditioned to receive data when enabled through the command register. The receiver looks for a High-to-Low (mark-to-space) transition of the start bit on the RxD input pin. If a transition is detected, the state of the RxD pin is sampled each 16X clock for 7-1/2 clock periods (16X clock mode) or at the next rising edge of the bit time clock (1X clock mode). If RxD is sampled high, (that is the start bit was low less than 7/16 to 1/2 bit time) the start bit is judged invalid and the search for another valid start bit begins immediately. If RxD is still low, a valid start bit is assumed and the receiver then continues to sample the input at one-bit time intervals at the theoretical center of the bit. When the proper number of data bits and parity bit (if used) have been assembled, and one half-stop bit has been detected the receiver loads the byte to the FIFO. The least significant bit is received first. The data is then transferred to the Receive FIFO and the ISR RxRDY bit in the SR is set to a 1. This condition can be programmed to generate an interrupt at IRQN or I/O[4:5] for channels A or B respectively. If the character length is less than 8 bits, the most significant unused bits in the RxFIFO are set to zero. After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero character was received with the stop bit at a zero level (framing error) and RxD remains Low for at least another one half bit time after the stop bit was sampled, then the receiver operates as if a new start bit had been detected. It then continues assembling the next character. The error conditions of parity error, framing error, and overrun error (if any) are written to the SR at the received character boundary. This is just before the RxRDY status bit is set. A break condition is detected when RxD is Low for the entire character including the parity bit, if used, and stop bit. When a break is found a character consisting of all zeros will be loaded into the RxFIFO, the received break bit in the SR and the "change of break" bit in the ISR are set to 1 and the receiver ready is set in the SR. The RxD input must return to high for two (2) clock edges of the RxC1x clock for the receiver to recognize the end of the break condition. At the end of the break condition the search for the next start bit begins. Two edges of the RxC1x clock will usually require a high time of one RxC1x clock period or 3 RxC1x edges since the clock of the controller is usually not synchronous to nor in phase with the RxC1x clock. Receiver Status Bits There are five (5) status bits that are evaluated with each byte (or character) received: received break, framing error, parity error, overrun error, and change of break. The first three are appended to each byte and stored in the RxFIFO. The last two are not necessarily related to the byte being received or a byte that is in the RxFIFO. They are however developed by the receiver state machine. The "received break" will always be associated with a zero byte in the RxFIFO. It means that zero character was a break character and not a zero data byte. The reception of a break condition will always set the "change of break" (see below) status bit in the Interrupt Status Register (ISR).
2000 Feb 10
11
Philips Semiconductors
Objective specification
Dual UART
SC28L202
The Change of break condition is reset by a reset error status command in the command register A framing error occurs when a non-zero character was seen and that character has a zero in the stop bit position. The parity error indicates that the receiver-generated parity was not the same as that sent by the transmitter. The framing, parity and received break status bits are reset when the associated data byte is read from the RxFIFO since these "error" conditions are attached to the byte that has the error The overrun error occurs when the RxFIFO is full, the receiver shift register is full, and another start bit is detected. At this moment the receiver has 257 valid characters and the start bit of the 258th has been seen. At this point the host has approximately 6/16 bit time to read a byte from the RxFIFO or the overrun condition will be set. The 258th character then overruns the 257th and the 258th the 259th and so on until an open position in the RxFIFO is seen. ("seen" meaning at least one byte was read from the RxFIFO.) Overrun is cleared by a use of the "error reset" command in the command register. The fundamental meaning of the overrun is that data has been lost. Data in the RxFIFO remains valid. The receiver will begin placing characters in the RxFIFO as soon as a position becomes vacant. NOTE: Precaution must be taken when reading an overrun FIFO. There will be 256th valid characters in the receiver FIFO. There will be one character in the receiver shift register. However it will NOT be known if more than one "over-running" character has been received since the overrun bit was set. The 257th character received and read as valid but it will not be known how many characters were lost between the two characters of the 256th and 257th reads of the RxFIFO. In the 8-bit mode, the numbers 8 and 9 replace the numbers 256 and 257 above. The "Change of break" means that either a break has been detected or that the break condition has been cleared. This bit is available in the ISR. The break change bit being set in the ISR and the received break bit being set in the SR will signal the beginning of a break. At the termination of the break condition only the change of break in the ISR will be set. After the break condition is detected the termination of the break will only be recognized when the RxD input has returned to the high state for two successive edges of the 1x clock; 1/2 to 1 bit time. (see above) The receiver is disabled by reset or via CR commands. A disabled receiver will not interrupt the host CPU under any circumstance in the normal mode of operation. If the receiver is in the multi-drop or special mode, it will be partially enabled and thus may cause an interrupt. Refer to section on Wake-Up and the register description for MR1 for more information. Receiver FIFO The receiver buffer memory is a 256 byte FIFO with three status bits appended to each data byte. (The FIFO is then 256 11-bit "words"). The receiver state machine gathers the bits from the receiver shift register and the status bits from the receiver logic and writes the assembled byte and status bits to the RxFIFO shortly after the stop bit has been sampled. Logic associated with the FIFO encodes the number of filled positions for presentation to the interrupt arbitration system. The encoding is always the number of filled positions. Thus, a full RxFIFO will bid with the value of 255 and the Status Register RxFULL bit is set. When empty it will not bit at all. One position occupied bids with the value 1. An empty FIFO will not bid since no character is available.
Normally RxFIFO will present a bid to the arbitration system whenever it has one or more filled positions. The bits of the RxFIFO Interrupt Offset Level (RxFIL) or the bits of the MR2(3:2) allow the user to modify this characteristic so that bidding will not start until one of four levels (one or more filled, 64 filled, 192 filled, full) have been reached. As will be shown later this feature may be used to make slight improvements in the interrupt service efficiency. A similar system exists in the transmitter. RxFIFO Status Bits. Status reporting modes This description applies to the upper three bits in the "Status Register" These three bits are not "in the status register"; they are part of the RxFIFO. The three status bits at the output of the RxFIFO are presented as the upper three bits of the status register included in each UART. The error status of a character, as reported by a read of the SR (status register upper three bits) can be provided in two ways, as programmed by the error mode control bit in the mode register: "Character mode " or the "Block Mode". The block mode may be further modified (via a CR command) to set the status bits as the characters enter the FIFO or as they are read from the FIFO. In the 'character' mode, status is provided on a character by character basis as the characters are read from the RxFIFO: the "status" applies only to the character at the output of the RxFIFO - The next character to be read. In the 'block' mode (on entry) the status provided in the SR for these three bits is the logical OR of the status for all characters coming to the input of the RxFIFO since the last reset error command was issued. In this mode each of the status bits stored in the RxFIFO are passed through a latch as they are sequentially written to the receiver FIFO. If any of the characters has an error bit set that latch will set and remain set until it is reset with a "receiver reset" issued from the command register or a chip reset is issued. The purpose of this mode is indicating an error in the data block as opposed to an error in a character. This mode improves receiver service efficiency. In modern systems with low error rates, it is more efficient to ask for retransmit of a block error data than to analyze it on a byte by byte system. The above paragraph describes the block mode activity as the data is entered to the RxFIFO. Normally the status would be read only once - at the beginning of the service to the receiver interrupt. If an error is not set then the entire amount of data in the RxFIFO would be read without any more reading if the receiver status. This effectively doubles the efficiency of reading the receiver RxFIFO. The use of the block mode on Exit passes the data and error conditions as the RxFIFO is read. Here the final read of the status register would be after the last byte was read from the RxFIFO. This delays the knowledge of an error condition until after the data has been read. The latch used in the block mode to indicate "problem data" is usually set as the characters are read out of the RxFIFO. Via a command in the CR the latch may be configured to set as error characters are loaded to the RxFIFO. This gives the advantage of indicating "problem data" up to 256 (or the FIFO size) characters earlier. In either mode, reading the SR does not affect the RxFIFO. The RxFIFO address is advanced only when the RxFIFO is read. Therefore, the SR should be read prior to reading the corresponding data character.
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
If the RxFIFO is full when a new character is received, the character is held in the receiver shift register until a position is available in the RxFIFO. At this time there are 257 valid characters in the RxFIFO. If an additional character is received while this state exists, the contents of the RxFIFO are not affected: the character previously in the shift register is lost and the overrun error status bit, SR [4], will be set upon receipt of the start bit of the new (overrunning) character. Wake Up Mode (Also the "9-bit", "multi-drop", "party; line" or Special mode) The SC28L202 provides four modes of this common asynchronous "party line" protocol where the parity bit is used to indicate that a byte is address data or information data. Three automatic modes and the default Host operated mode are provided. The automatic mode has several sub modes (see below). In the full automatic the internal state machine devoted to this function will handle all operations associated with address recognition, data handling, receiver enables and disables. In both modes the meaning of the parity bit is changed. It is often referred to as the A/D bit or the address/data bit - sometimes the "9th" bit. It is used to indicate whether the byte presently in the receiver shift register is an "address" byte or a "data" byte. A "1" usually means address, a "0" data. Its purpose is to allow several receivers connected to the same data source to be individually addressed. Of course addressing could be by group also. Normally the "Master" would send an address byte to all receivers "listening". The remote receiver will be "looking" at the data stream for its address. Upon recognition of its address it will enable itself to receive the following data stream. Upon receipt of an address not its own it would then disable itself. As descried below appropriate status bits are available to describe the operation. Again, for this mode an "address byte" is a byte that has the bit in the parity position set to logical 1. The use of the multi-drop mode usually implies a "master and slave" configuration of the several UART stations so programmed. The software control should allow time for the slave stations to respond to the receipt of an address bit. Often a reply from the addressed station is expected to confirm the receipt of the address. Please see control the automatic features of the address recognition in MR0(1:0). Enabling the Wake Up mode (This mode is variously referred to as "9-bit" or "Multi-drop".) This mode is selected by programming bits MR1 [4:3] (the parity bits) to '11'. The wake up feature has four modes of operation: one strictly under processor control and three automatic. These modes are controlled by bits 6, 1, 0 in the MR3 register. Bit 6 controls the loading of the address byte to the RxFIFO and MR0 [1:0] determines the sub mode as shown in the following list. MR3 [1:0] = 00 Normal Wake Up Mode (default) which is the same as previous DUARTs and is therefore controlled by the processor. The Host controls operation via interrupts it receives and commands it writes to the DUART command registers (CR). Normal Wake up (The default configuration) The enabling of the wake-up mode executes a partial enabling of the receiver state machine. Even though the receiver has been reset the wake up mode will over ride the disable and reset condition. In the default (mode "00" above and the least efficient) configuration for this mode of operation, a 'master' station transmits an address character followed by data characters for the addressed 'slave' station. The slave stations, whose receivers are normally disabled
(not reset), examine the received data stream. Upon recognition of its address bit (this is the parity bit redefined to indicate the associated byte is an address bye - not the address itself) interrupts the CPU (by setting RxRDY). The CPU (host) compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. Upon receipt of another address character, the CPU may disable the receiver to initiate the process again. A transmitted character consists of a start bit; the programmed number of data bits, an address/data (A/D) bit and the programmed number of stop bits. The CPU selects the polarity of the transmitted A/D bit by programming bit MR1 [2]. MR1 [2] = 0 transmits a zero in the A/D bit position which identifies the corresponding data bits as data. MR1 [2] = 1 transmits a one in the A/D bit position which identifies the corresponding data bits as an address. The CPU should program the mode register prior to loading the corresponding data bytes into the TxFIFO. While in this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RxFIFO if the received A/D bit is a one, but discards the received character if the received A/D bit is a zero. If the receiver is enabled, all received characters are transferred to the CPU via the RxFIFO. In either case when the address character is recognized the data bits are loaded into the data FIFO while the A/D bit is loaded into the status FIFO position normally used for parity error (SR [5]). Framing error, overrun error, and break detect operate normally whether or not the receiver is enabled. When the automatic modes are in operation the loading of the address character to the FIFO is controlled by the MR0 (6) bit. The several automatic controls. These modes are concerned with the recognition of the address character itself
* MR3 [1:0] = 01 Auto wake. Enable receiver on address
recognition for this station. Upon recognition of its assigned address the local receiver will be enabled by the character recognition state machine and normal receiver communications with the host will be established.
* MR3 [1:0] = 10 Auto Doze. Disable receiver on address
recognition, not for this station. Upon recognition of an address character that is not its own, in the Auto Doze mode, the receiver will be disabled by the character recognition state machine and the address just received either discarded or loaded to the RxFIFO depending on the programming of MR0 [6].
* MR3 [1:0] = 11 Auto wake and doze. Both modes described
above. The programming of MR3 [1:0] to 11 will enable both the auto wake and auto doze features. The enabling of the wake-up mode executes a partial enabling of the receiver state machine. Even though the receiver has been reset the wake up mode will over ride the disable and reset conditions. Receiver Reset and Disable Receiver disable stops the receiver immediately - data being assembled in the receiver shift register is lost. Data and status in the FIFO is preserved and may be read. A re-enable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected. Receiver reset will discard the present shift register data, reset the receiver ready bit (RxRDY), clear the status of the byte at the top of
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13
Philips Semiconductors
Objective specification
Dual UART
SC28L202
the FIFO and re-align the FIFO read/write pointers. This effectively "clears" the receiver FIFO although the FIFO data is not altered. Receiver Watchdog Timer A `watchdog timer' is associated with each receiver. Its interrupt is enabled by the "watchdog" bits of the "Watch Dog, Character Address, and X enable" register (WCXER). The purpose of this timer is to alert the control processor that characters are in the RxFIFO which have not been read and/or the data stream has stopped. This situation may occur at the end of a transmission when the last few characters received are not sufficient to cause an interrupt. This counter times out after 64 bit times. It is reset each time a read of the RxFIFO is executed. Receiver Time-out Mode In addition to the watch dog timer described in the receiver section, the counter/timer may be used for a similar function. Its programmability, of course, allows much greater precision of timeout intervals. The time-out mode uses the received data stream to control the counter. Each time a received character is transferred from the shift register to the RxFIFO, the counter is restarted. If a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. This mode can be used to indicate when data has been left in the RxFIFO for more than the programmed time limit. Otherwise, if the receiver has been programmed to interrupt the CPU when the receive FIFO is full, and the message ends before the FIFO is full, the CPU may not know there is data left in the FIFO. The CTPU and CTPL value would be programmed for just over one character time, so that the CPU would be interrupted as soon as it has stopped receiving continuous data. This mode can also be used to indicate when the serial line has been marking for longer than the programmed time limit. In this case, the CPU has read all of the characters from the FIFO, but the last character received has started the count. If there is no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated. Writing the appropriate command to the command register enables the time-out mode. Writing an `Ax' to CR A or CR B will invoke the time-out mode for that channel. Writing a 0xCx to CR A or CR B will disable the time-out mode. CTPU and CTPL should be loaded with a count-down value that, with the selected clock, will generate a time period greater than the normal receive character period. The time-out mode disables the regular START/STOP Counter commands and puts the C/T into counter mode under the control of the received data stream. Each time a received character is transferred from the shift register to the RxFIFO, the C/T is stopped after 1 C/T clock, reloaded with the value in CTPU and CTPL and then restarted on the next C/T clock. If the C/T is allowed to end the count before a new character has been received, the counter ready bit, ISR [3], will be set. If IMR [3] is set, interrupt arbitration for the C/T will begin. Invoking the `Set Time-out Mode On' command, CRx = `Ax', clears the counter ready bit and stop the counter until the next character is received. Exiting the time mode will clear the counter ready bit. Arbitrating Interrupt Structure (NOTE: The advantages and intelligence of this system may be completely defeated by merely setting the arbitration value in the ICR to 0x00 and not using the CIR. One would then rely on traditional interrupt service by searching and testing various status registers on the assertion of the IRQN.) The interrupt system determines when an interrupt should be asserted thorough an arbitration (or bidding) system. This arbitration
is exercised over the several systems within the DUART that may generate an interrupt. These will be referred to as "interrupt sources". There are 18 in all and may of those have several sub-levels. In general the arbitration is based on the fill level of the receiver FIFO or the empty level of the transmitter FIFO. The FIFO levels are encoded into an 8-bit number, which is concatenated to the channel number and source identification code. All of this is compared (via the bidding or arbitration process) to a user defined "threshold". Whenever a source exceeds the numerical value of the threshold the interrupt will be generated. Interrupt sources that do not have a FIFO are each provided with a "programmable field" that will determine their importance in the arbitration and type identification process. (See Table 1 below) At the time of interrupt acknowledge (IACKN) the source which has the highest bid (not necessarily the source that caused the interrupt to be generated) will be captured in a "Current Interrupt Register" (CIR). This register will contain the complete definition of the interrupting source: channel, types of interrupt (receiver, transmitter, change of state, etc.) and FIFO fill level. The value of the bits in the CIR are used to drive the interrupt vector and global registers such that controlling processor may be steered directly to the proper service routine. A single read operation to the CIR provides all the information needed to qualify and quantify the most common interrupt sources.
* Transmit FIFO empty level for each channel * Receive FIFO Fill level for each channel * Receiver with error for each channel * Change in break received status per channel * Change of state on channel input pins * Receiver Watch-dog Time out Event * Xon/Xoff character recognition * Address character recognition * Counter-Timer * No interrupt active (very useful in polled service and as a test
value to terminate interrupt service) Associated with the interrupt system are the interrupt mask register (IMR) and the interrupt status register (ISR) resident in each UART. Programming of the IMR selects which of the above sources may enter the arbitration process. The IMR enables the interrupt. Only the bidders in the ISR whose associated bit in the IMR is set to one (1) will be permitted to enter the arbitration process. The ISR can be read by the host CPU to determine all currently active interrupting conditions. For convenience of reading the ISR the MR1 (6) bit, when set, allows the reading of the ISR masked by the bits of the IMR. Enabling and Activating Interrupt sources An interrupt source becomes enabled when writing a one to the proper Interrupt Mask Register bit (IMR) activates its interrupt capability. An interrupt source can never generate an IRQN or have its "bid" or interrupt number appear in the CIR unless the source has been enabled by the appropriate bit in an IMR. An interrupt source is active if it is presenting its bid to the interrupt arbiter for evaluation. Most sources have simple activation requirements. The watch-dog timer, break received, Xon/Xoff or
The interrupt sources for each channel are listed below.
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14
Philips Semiconductors
Objective specification
Dual UART
SC28L202
Address Recognition and change of state interrupts become active when the associated events occur and the arbitration value generated thereby exceeds the threshold value programmed in the ICR (Interrupt Control Register). The transmitter and receiver functions have additional controls to modify the condition upon which the initiation of interrupt "bidding" begins: the TxINT and RxINT fields of the MR0 and MR2 registers. These fields can be used to start bidding or arbitration when the RxFIFO is not empty, 50% full, 75% full or 100% full. For the transmitter it is not full, 50% empty, 75% empty and empty. Example: To increase the probability of transferring the contents of a nearly full RxFIFO, do not allow it to start bidding until 50% or 75% full. This will prevent its relatively high priority from winning the arbitration process at low fill levels. A high threshold level could accomplish the same thing, but may also mask out low priority interrupt sources that must be serviced. Note that for fast channels and/or long interrupt latency times using this feature should be used with caution since it reduces the time the host CPU has to respond to the interrupt request before receiver overrun occurs. Setting interrupt priorities The bid or interrupt number presented to the interrupt arbiter is composed of character counts, channel codes, fixed and programmable bit fields. The interrupt values are generated for various interrupt sources as shown in Table 1. The value represented by the bits 11 to 4 in Table 1 are compared against the value represented by the "Threshold. The "Threshold", bits 10 to 0 of the ICR (Interrupt Control Register), is aligned such that bit 0 of the threshold is compared to bit 1 of the interrupt value generated by any of the sources. Whenever the value of the interrupt source is greater than the threshold the interrupt will be generated. The channel number arbitrates only against other channels. The threshold is not used for the channel arbitration. This results in
channel B having the highest arbitration number. The decreasing order is B to A. If all other parts of an arbitration cycle are equal then the channel number will determine which channel will dominate in the arbitration process. Note several characteristics of Table 1 in bits 4:1. These bits contain the identification of the bidding source as indicated below:
* 0000 No interrupt source active * x001 Receiver without error * x101 Receiver with error (errors are: parity, framing and * overrun. Break is not considered an error * x010 Transmitter * 1110 Change of Break * 0110 Change of State on I/O Ports * 0111 Xon/Xoff Event * 1011 Address Recognition * x100 Receiver watch dog * 1000 Counter timer * 1111 Rx Loop Back Error
The codes form bits 4:1 drive part of the interrupt vector modification and the Global Interrupt Type Register. The codes are unique to each source type and identify them completely. The channel numbering progresses from "A" to "B" as the binary numbers 0 to 1 and identify the interrupting channel uniquely. As the channels arbitrate "B" will have the highest bidding value and "A" the lowest
Table 1. Interrupt Values
Type Receiver w/o error Receiver w/ error Receiver Watch-dog Transmitter Change of Break Rx Loop Back Error Change of State Xon/Xoff Counter timer Address Recognition No interrupt Threshold Bit 11:4 RxFIFO filled Byte Count RxFIFO filled Byte Count RxFIFO filled Byte Count TxFIFO empty Byte Count Programmed Field Programmed Field Programmed Field Programmed Field Programmed Field Programmed Field 0 Bits 7:0 of Interrupt Control Register (ICR) 1 1 0 0 1 1 0 0 Bit 3 0 1 1 0 1 1 1 1 0 0 0 0 Bit 2 0 0 0 1 1 1 1 1 0 1 0 0 Bit 1 1 1 0 0 0 1 0 1 0 1 0 0 0 Bit 0 Channel No. Channel No. Channel No. Channel No. Channel No. Channel No. Port 0 or 1 Channel No. Counter 0 or 1 Channel No.
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
Interrupt Arbitration and IRQN generation Interrupt arbitration is the process used to determine that an interrupt request should be presented to the host. The arbitration is carried out between the "Interrupt Threshold" and the "sources" whose interrupt bidding is enabled by the IMR. The interrupt threshold is part of the ICR (Interrupt Control Register) and is a value programmed by the user. The "sources" present a value to the interrupt arbiter. That value is derived from four fields: the channel number, type of interrupts source, FIFO fill level, and a programmable value. The interrupt request (IRQN) will be asserted only when one or more of these values exceeds the threshold value in the interrupt control register will. Following assertion of the IRQN the host will either assert IACKN (Interrupt Acknowledge) or will use the command to "Update the CIR". At the time either action is taken the CIR will capture the value of the source that is prevailing in the arbitration process. (Call this value the winning bid). The Sclk drives the arbitration process. It evaluates the 12 bits of the arbitration bus at 1/2 the Sclk rate developing a value for the CIR every two Sclk cycles. New arbitration values presented to the arbitration block during an arbitration cycle will be evaluated in the next arbitration cycle. For sources other than receiver and transmitters the user may set the high order bits of an interrupt source's bid value, thus tailoring the relative priority of the interrupt sources. The fill level of their respective FIFOs controls the priority of the receivers and transmitters. The more filled spaces in the RxFIFO the higher the bid value; the more empty spaces in the TxFIFO the higher its priority. Channels whose programmable high order bits are set will be given interrupt priority higher than those with zeros in their high order bits, thus allowing increased flexibility. The transmitter and receiver bid values contain the character counts of the associated FIFOs as high order bits in the bid value. Thus, as a receiver's RxFIFO fills, it bids with a progressively higher priority for interrupt service. Similarly, as empty space in a transmitter's TxFIFO increases, its interrupt arbitration priority increases. The programmable fields allow the software to adjust the authority or value of the bid for those devices not having a FIFO. For example: The break condition is sometimes used to signal a starting point in a continuous stream of data. A Continuous running weather report or stock market "ticker-tape" report needs breaks in the data so that a receiver knows where the data starts. Once start of the break is detected it is important to reset the "change of break " interrupt so that this bit can signal the condition of the break ending. This is signaled by the `L202 the setting another change of break event in the ISR. Since it is assumed the data will be starting very soon after the end of break it is important to give the change of break condition a high priority. This may be accomplished by setting the arbitration value for the "change of break" to a high value. The value in the "change of break programmable field" in Table 1 would be 0x7F. IACKN Cycle, Update CIR When the host CPU responds to the interrupt, it will usually assert the IACKN signal low. This will cause the DUART to generate an IACKN cycle in which the condition of the interrupting device is determined. When IACKN asserts, the last valid interrupt number is captured in the CIR. The value captured presents most of the important details of the highest priority interrupt at the moment the IACKN (or the "Update CIR" command) was asserted. The Dual UART will respond to the IACKN cycle with an interrupt vector. The interrupt vector may be a fixed value, the content of the 2000 Feb 10 16
Interrupt Vector Register, or when "Interrupt Vector Modification" is enabled via ICR, it may contain codes for the interrupt type and/or interrupting channel. This allows the interrupt vector to steer the interrupt service directly to the proper service routine. The interrupt value captured in the CIR remains until another IACKN cycle occurs or until an "Update CIR" command is given to the DUART. The interrupting channel and interrupt type fields of the CIR set the current "interrupt context" of the DUART. The channel component of the interrupt context allows the use of Global Interrupt Information registers that appear at fixed positions in the register address map. For example, a read of the Global RxFIFO will read the channel B RxFIFO if the CIR interrupt context is channel B receiver. At another time read of the GRxFIFO may read the channel A RxFIFO (CIR holds a channel A receiver interrupt) and so on. Global registers exist to facilitate qualifying the interrupt parameters and for writing to and reading from FIFOs without explicitly addressing them. The CIR will load with x'00 if IACKN or Update CIR is asserted when the arbitration circuit is NOT asserting an interrupt. In this condition there is no arbitration value that exceeds the threshold value. When Interrupt vector modification is active in this situation the interrupt vector bits associated with the CIR will all be zero. Global Registers The "Global Registers", 10 in all, are driven by the interrupt system. They are defined by the content of the CIR (Current Interrupt Register) as a result of an interrupt arbitration. In other words they are indirect registers pointed to by the content of the CIR. The list of global register follows:
* GIBCR * GICR * GITR * GRxFIFO * GTxFIFO
The byte count of the interrupting FIFO Channel number of the interrupting channel Type identification of interrupting channel Pointer to the interrupting receiver FIFO Pointer to the interrupting transmitter FIFO
A read of the GRxFIFO will give the content of the RxFIFO that presently has the highest bid value. The purpose of this system is to enhance the efficiency of the interrupt system. The global registers and the CIR update procedure are further described in the Interrupt Arbitration system Polling, (Normal and using the CIR) Many users prefer polled to interrupt driven service where there are not a large number of fast data channels and/or the host CPU's other interrupt overhead is low. The Dual UART is functional in this environment. The most efficient method of polling is the use of the "update CIR" command (with the interrupt threshold set to zero) followed by a read of the CIR. This dummy write cycle will perform the same CIR capture function that an IACKN falling edge would accomplish in an interrupt driven system. A subsequent read of the CIR, at the same address, will give information about an interrupt, if any. If the CIR type field contains 0s, no interrupt is awaiting service. If the value is non-zero, the fields of the CIR may be decoded for type; channel and character count information. Optionally, the global interrupt registers may be read for particular information about the interrupt status or use of the global RxD and TxD registers for data transfer as appropriate. The interrupt context will remain in the CIR until another update CIR command or an IACKN cycle is initiated by the host CPU occurs. The CIR loads with x'00 if Update CIR is asserted when the arbitration circuit has NOT detected an arbitration value that exceeds the threshold value of the ICR. The global registers and CIR may be used as "vectors" to the service type required.
Philips Semiconductors
Objective specification
Dual UART
SC28L202
Traditional methods of polling status registers may also be used. Their lower efficiency may be greatly offset by use of the UCIR command and the read of the CIR. They reduce the many reads and tests of status registers to only one read and one write. This would normally be accomplished by setting the interrupt threshold to zero. Then the moment any system within the DUART needs service the next poll of the CIR would return a non zero value and the type field will inform the processor which of the possible 18 systems needs service. In the case of the FIFOs the number of bytes to be written or read is also available. Character and Address Recognition (Also used for Multi-drop, Xon/Xoff systems) Character recognition is specific to each of the two UARTs. Three programmable characters are provided for the character recognition for each channel. The three are general purpose in nature and may be set to only cause an interrupt or to initiate some rather complex operations specific to "Multi-drop" address recognition or in-band Xon/Xoff flow control. Character recognition system continually examines the incoming data stream. Upon the recognition of a character bits appropriate for the character recognized are set in the Xon/Xoff Interrupt Status Register (XISR) and in the Interrupt Status Register (ISR). The setting of these bit(s) will initiate any of the automatic sequences or and/or an interrupt that may have enabled via the MR0 register. NOTE: Reading the XISR Clears the status bits associated with the recognition. The characters of the recognition system are fully programmable. The Xon/Xoff characters will be set to the standard characters if the hardware or software reset is used. The character recognition circuits are basically designed to provide general-purpose character recognition. Additional control logic has been added to allow for Xon/Xoff flow control and for recognition of the address character in the multi-drop or "wake-up" mode. This logic also allows for the generation of interrupts in either the general-purpose recognition mode or the specific conditions mentioned above. The generality of the above provides a modicum of compatibility to BOP (Bit Oriented Protocol) where the generation and detection of "flags" is required. Parts of usually synchronous BOP protocols (HDLC in particular) are beginning to show up in asynchronous formats. Character Stripping The MR0 register provides for stripping the characters used for character recognition. Recall that the character recognition may be conditioned to control several aspects of the communication. However this system is first a character recognition system. The status of the various states of this system is reported in the XISR and ISR registers. The character stripping of this system allows for the removal of the specified control characters from the data stream: two for the Xon /Xoff and one for the wake up. Via control in the MR0 register these characters may be discarded (stripped) from the data stream when the recognition system "sees" them or they may be sent on the RxFIFO. Whether they are stripped or not the recognition system will process them according to the action requested; flow control, wake up, interrupt generation, etc. Care should be exercised in programming the stripping option if noisy environments are encountered. If a normal character were corrupted to a Xoff character the transmitter would be stopped. If that character were now stripped from the FIFO stack, then that stripping
action would make it difficult to determine the cause of transmitter stopping. When character stripping is invoked and a recognition character is received that has an error bit set that character is sent to the RxFIFO even though character stripping is active. Flow Control (Xon/Xoff) This section describes in-band flow control or Xon/Xoff signaling. For the RTS/CTS hardware (out-of-band) control see MR1(7) and MR2(4) descriptions. The flow control is accomplished via the character recognition system giving recognition information to the flow control processor. Xon and Xoff are special characters used by a receiver to start and stop the remote transmitter that is sending it data. As described below several modes of manual and automatic flow control are available by program control. The modes of control are described in MR3(3:2)
* 00 = Host mode * 01 = Auto transmit * 10 = Auto Receive * 11 = Auto receive and transmit
Mode control Xon/Xoff mode control is accomplished via the MR0. Bits 3 and 2 reset to zero resulting in all Xon/Xoff processing being disabled. If MR0 [2] is set, Xon/Xoff characters received may gate the transmitter. If MR0 [3] is set, the transmitter will transmit Xon and Xoff when triggered by attainment of fixed fill levels in the channel RxFIFO. The MR0 [7] bit also has a Xon/Xoff function control. If this bit is set, a received Xon or Xoff character is not loaded into the RxFIFO. If cleared, the power-on and reset default, the received Xon or Xoff character is loaded onto the RxFIFO for examination by the host CPU. The MR0 (7) function operates regardless of the value in MR0 (3:2) Xon Xoff Characters The programming of these characters is usually done individually. The standard Xon/Xoff characters are . Xon is 0x11, Xoff 0x13. Any enabling of the Xon/Xoff functions will use the contents of the Xon and Xoff character registers as the basis on which recognition is predicated. Host mode When neither the auto-receiver or auto-transmitter modes are set, the Xon/Xoff logic is operating in the host mode. In host mode, all activity of the Xon/Xoff logic is initiated by commands to the CRx. The Xoff command forces the transmitter to disable exactly as though a Xoff character had been received by the RxFIFO. The transmitter will remain disabled until the chip is reset or the CR (7:3) = 10110 (Xoff resume) command is given. In particular, reception of a Xon or disabling or re-enabling the transmitter will NOT cause resumption of transmission. Redundant CRTX-- commands, i.e. CRTXon, CRTXon, are harmless, although they waste time. A CRTXon may be used to cancel a CRTXoff (and vice versa) but both may be transmitted depending on the command timing with respect to that of the transmitter state machine. Auto-transmitter mode When a channel receiver loads a Xoff character into the RxFIFO, the channel transmitter will finish transmission of the current character and then stop transmitting. A transmitter so idled can be restarted by the receipt of a Xon character by the receiver or by a hardware or
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
software reset. The last option results in the loss of the untransmitted contents of the TxFIFO. When operating in this mode the Command Register commands for the transmitter are not effective. While idle data may be written to the TxFIFO and it continue to present its fill level to the interrupt arbiter and maintains the integrity of its status registers. Use of '00' as a Xon/Xoff character is complicated by the Receiver break operation which loads a '00' character on the RxFIFO. The Xon/Xoff character detectors do not discriminate in this case from a Xon/Xoff character received through the RxD pin. NOTE: To be recognized as a Xon or Xoff character, the receiver must have room in the RxFIFO to accommodate the character. An Xon/Xoff character that is received resulting in a receiver overrun does not effect the transmitter nor is it loaded into the RxFIFO, regardless of the state of the Xon/Xoff transparency bit, MR0 (7). Receiver Mode Since the receiving FIFO resources in the Dual UART are limited, some means of controlling a remote transmitter is desirable in order to lessen the probability of receiver overrun. The Dual UART provides two methods of controlling the data flow. There is a hardware-assisted means of accomplishing control, the so-called out-of-band flow control, and an in-band flow control method. The out-of-band flow control is implemented through the CTSN-RTSN signaling via the I/O ports. The operation of these hardware handshake signals is described in the receiver and transmitter discussions. In-band flow control is a protocol for controlling a remote transmitter by embedding special characters within the message stream, itself. Two characters, Xon and Xoff, which do not represent normal printable character take on flow control definitions when the Xon/Xoff capability is enabled. Flow control characters received may be used to gate the channel transmitter on and off. This activity is referred to as Auto-transmitter mode. To protect the channel receiver from overrun, fixed fill levels (hardware set at 240 characters) of the RxFIFO may be employed to automatically insert Xon/Xoff characters in the transmitter's data stream. This mode of operation is referred to as auto-receiver mode. Commands issued by the host CPU via the CR can simulate all these conditions. Auto Receive and Transmit This is a combination of both modes. NOTE: Xon /Xoff characters The Xon/Xoff character with errors will be accepted as valid. The user has the option sending or not sending these characters to the FIFO. Error bits associated with Xon/Xoff will be stored normally to the receiver FIFO. The channel's transmitter may be programmed to automatically transmit a Xoff character without host CPU intervention when the RxFIFO fill level exceeds a fixed limit (240). In this mode it will transmit a Xon character when the RxFIFO level drops below a second fixed limit (16). A character from the TxFIFO that has been loaded into the TxD shift register will continue to transmit. Character(s) in the TxFIFO that have not been loaded to the transmitter shift register are unaffected by the Xon or Xoff transmission. They will be transmitted after the Xon/Xoff activity concludes. If the fill level condition that initiates Xon activity negates before the flow control character can begin transmission, the transmission of
the flow control character will not occur. That is, either of the following sequences may be transmitted depending on the timing of the FIFO level changes with respect to the normal character times: Fix This Character Character Xoff Character Xon Character
Hardware keeps track of Xoff characters sent that are not rescinded by a Xon. This logic is reset by writing MR0 (3) to '0'. If the user drops out of Auto-receiver mode while the XISR shows Xoff as the last character sent the Xon/Xoff logic would not automatically send the negating Xon. The kill CRTX command (of the command register) can be used to cleanly terminate any pending CRTX commands. NOTE: In no case will a Xon/Xoff character transmission be aborted. Once the character is loaded into the TX Shift Register, transmission continues until completion or a chip reset or transmitter reset is encountered. The kill CRTX command has no effect in either of the Auto modes. Xon/Xoff Interrupts The Xon/Xoff logic generates interrupts only in response to recognizing either of the characters in the XonCR or XoffCR (Xon or Xoff Character Registers). The transmitter activity initiated by the Xon/Xoff logic or any CR command does not generate an interrupt. The character comparators operate regardless of the value in MR0 (3:2). Hence the comparators may be used as general-purpose character detectors by setting MR0 (3:2)='00' and enabling the Xon/Xoff interrupt in the IMR. The Dual UART can present the Xon/Xoff recognition event to the interrupt arbiter for IRQN generation. The IRQN generation may be masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid level of a Xon/Xoff recognition event is controlled by the Bidding Control Register X, BCRx, of the channel. The interrupt status can be examined in ISR [4]. If cleared, no Xon/Xoff recognition event is interrupting. If set, a Xon or Xoff recognition event has been detected. The X Interrupt Status Register, XISR, can be read for details of the interrupt and to examine other, non-interrupting, status of the Xon/Xoff logic. Refer to the XISR in the Register Descriptions. The character recognition function and the associated interrupt generation is disabled on hardware or software reset. Multi-drop or Wake up or 9 bit mode This mode is used to address a particular UART among a group connected to the same serial data source. Normally it is accomplished by redefining the meaning of the parity bit such that it indicates a character as address or data. While this method is fully supported in the SC28L202 it also supports recognition of the character itself. Upon recognition of its address the receiver will be enabled and data loaded onto the RxFIFO. Further the Address recognition has the ability, if so programmed, to disable (not reset) the receiver when an address is seen that is not recognized as its own. The particular features of "Auto Wake and Auto Doze" are described in the detail descriptions under "Receiver Operation" above. NOTE: Care should be taken in the programming of the character recognition registers. Programming x'00, for example, may result in a break condition being recognized as a control character. This will be further complicated when binary data is being processed.
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18
Philips Semiconductors
Objective specification
Dual UART
SC28L202
PROGRAMMING THE HOST INTERFACE
Writing control words into the appropriate registers programs the operation of the DUART. Operational feedback is provided via status registers that can be read by the CPU. The addressing of the registers is described in the Register Map. The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems. For example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the ACR should only be made while the C/T is stopped. Each channel has 3 mode registers (MR0, 1, 2) which control the basic configuration of the channel. Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. Refer to Table 2 for register bit descriptions.
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19
Philips Semiconductors
Objective specification
Dual UART
SC28L202
REGISTER DESCRIPTION AND PROGRAMMING NOTE
Programmers may use either of two register sets or mix the features of each. It is suggested that only the extended register set be used in new designs. However if a system needed to use a block of communications code written for an older system then that code could merely be called. This is similar to calling a DOS(R) program in a WINDOWS(R) environment. Before calling legacy code it is recommended (but not required) to execute "Reset to C92" command. Also consideration must be given to the I/O pins to avoid contention of drivers of the pins and an external driver. Two control register descriptions and maps are implemented in the SC28L92: one represents the previous 4-bit address and the other the new 7-bit address space representing the all the new features of the new design. The Design of the SC28L202 allows for high degree with former Philips two channel communications controllers - DUARTs. To
facilitate this feature the complete register function and control of the SC26C92 is replicated in the SC28L202. That is code written for the SCN2681, SCN68681, SCC2692, SCC68692 and SC26C92 will operate with this device. With the execution of code written for previous DUARTs and immediately after a hardware reset or a "Reset to C92" command the following configuration will exist: 1. The size of all FIFOs is set to 8 bytes (for legacy code). 2. FIFO interrupt levels are controlled by the bits of the MR registers 3. All I/O ports are set to input. 4. Receiver FIFO set to interrupt on FIFO ready. 5. Transmitter FIFO set to interrupt on FIFO empty. 6. Baud selection follows previous 4 bit programming and baud rate grouping controlled by the MR and ACR registers.
Table 2. SC28L202 REGISTER BIT DESCRIPTIONS Registers that control Global Properties of the 28L202
GCCR - Global Configuration Control Register THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION. Hex Addr Bit (7) Reserved Bit (6) DACKN Assertion 0 - Slow (timed by 2 SCLK edges) 1 - Fast (Asynchronous) Bit (5:3) Reserved Bit(2:1) IVC Interrupt Vector Control 00 = no interrupt vector 01 = IVR(7:0) 10 = IVR(7:1) + channel code 11 = IVR(7:5) + interrupt type + channel code BIT 0 ISR Read Mode 0 = ISR Unmasked 1 = ISR Read Masked by IMR
Set to 0
GCCR(7:6) DACKN Assertion Motorola bus cycle time can be controlled by selecting a DACKN assertion time based on X1/Sclk speed . See examples below. X1/SCLK 3.6864 MHz 7.3728 MHz 14.7456 MHz 29.4912 MHz 33.1776 MHz 44.2368 MHz GCCR(5:3): Reserved GCCR(2:1): Interrupt vector configuration The IVC field controls if and how the assertion of IACKN (the interrupt acknowledge pin) will form the interrupt vector for the SFSR A and B Special Feature & Status Register Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved BIT 4 Reserved #SCLK Cycles 1/2-1 1/2-1 1/2-1 1-2 2-3 2-3 Delay 136-272 ns 68-136 ns 34-68 ns 34-68 ns 60-90 ns 46-68 ns
DUART. If b'00, no vector will be presented during an IACKN cycle. The bus will be driven high (0xFF). If the field contains a b'01, the contents of the IVR, Interrupt Vector Register, will be presented as the interrupt vector without modification. If IVC = 0x10, the channel code will replace the LSB of the IVR; if IVC = b'11 then a modified interrupt type and channel code replace the 3 LSBs of the IVR. NOTE: The modified type field IVR(2:1) is:
* 10 Receiver w/o error * 11 Receiver with error * 01 Transmitter * 00 All remaining sources
GCCR(0): Interrupt Status Masking This bit controls the readout mode of the Interrupt Status Register, ISR. If set, the ISR reads the current status masked by the IMR, i.e. only interrupt sources enabled in the IMR can ever show a '1' in the ISR. If cleared, the ISR shows the current status of the interrupt source without regard to the Interrupt Mask setting.
BIT 3 Loop Back Error 0 = No 1 = Yes (read Only)
BIT 2:1 Remote Loop Error Check 00 = Disabled 01 = Enabled, RxC c TxC 10 = Enabled, RxC c TxCN
BIT 0 Reserved
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
SFSR(7:4) Reserved SFSR(3) Status of loop back error check. A "1" indicates a loop back error occurred, which will be entered for interrupt arbitration. It can be cleared by the processor by a write to this register with D(3) equal to "1". SFSR(2:1) Certification of returned data as Valid (This feature implies the transmitted data is being returned by the remote receiver. ) Sets automatic checking of returned data. This mode stores transmitted data and compares it to data returned from the remote receiver. It is used where relative short delay times are available, up TRR Test and Revision Register. TRR Bit 7 Test 2 Bit 6:0 Revision Code
to two characters in time . This mode will totally relieve the processor of this task where certainty of transmission and reception is required. The transmitted data is looped back by the remote station with a half-bit time delay. The local transmitted data is internally sent to the local receiver for comparison. An interrupt is generated in the case of an error (data mismatch, parity or framing). 00 = The checking is disabled 01 = Return data is clocked in on rise of TxC 10 = Return data is clocked on of rise of TxCN 00 = Reserved SFSR(0) Reserved
TRR(7) Test 2 Enable Bypass divide by 16 counter in all TxC and RxC.
TRR [6:0] - Chip Revision Code Indicates the revision of the chip. Initial code will be 0000000. The revision code bits (6:0) are hard wired. The default setting of the test bits is all zero.
STCR - Scan Test Control Register. Addr 77 STCR(0) Iddq Test - Turns off all pull-up devices on the I/O pins. SES - System Enable Status Register, A and B Bit 7 Reserved Set to 0 Bit 6 Reserved Set to 0 Bit 5 Transmitter Enabled 0 = No 1 = Yes Bit 4 Receiver Enabled 0 = No 1 = Yes Bit 3 Watch Dog Timer 0 = No 1 = Yes Bit 2 Address Recognition 0 = No 1 = Yes Bit 1 Xon 0 = No 1 = Yes Bit 0 Xoff 0 = No 1 = Yes BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Memory Test BIT 1 Scan Test BIT 0 Iddq Test
This register reports the enabled status of the several sub systems in the DUART. These systems are sometimes controlled by the state machines of the receiver FIFOs. EOS - Enhanced Operation Status Register Bit 7 Reserved Bit 6 I/O Port Operation Bit 5 Reserved Bit 4 Counter/Timer 0 Clock Select Bit 3 Channel B Rx/Tx Clock Selection 0 = Default 1 = Enhanced Bit 2 Channel A Rx/Tx Clock Selection 0 = Default 1 = Enhanced Bit 1 Channel B FIFO Interrupt Level Control 0 = Default 1 = Enhanced Bit 0 Channel A FIFO Interrupt Level Control 0 = Default 1 = Enhanced
0 = Default 1 = Enhanced
0 = Default 1 = Enhanced
This register reports the status of the Enhanced operation in several sub systems in the DUART.
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21
Philips Semiconductors
Objective specification
Dual UART
SC28L202
UART Registers
These registers are generally concerned with formatting, transmitting and receiving data. The user must exercise caution when changing the mode of running receivers, transmitters, PBRG or counter/timers. The selected mode will be activated immediately upon selection, even if this occurs during the reception or transmission of a character. It is also possible to disrupt internal controllers by changing modes at critical
times, thus rendering later transmission or reception faulty or impossible. An exception to this policy is switching from auto-echo or remote loop back modes to normal mode. If the deselecting occurs just after the receiver has sampled the stop bit (in most cases indicated by the assertion of the channel's RxRDY bit) and the transmitter is enabled, the transmitter will remain in auto-echo mode until the end of the transmission of the stop bit.
MR0 - Mode Register 0, A and B MR0 can be accessed directly at H'20" and H'28" in the Extended section of the address map, or by means of the "MR Pointers" at the 0x00 and 0x08 address pointers used by legacy code. (TEST 1) (TEST 3) Bit 7 Rx Watchdog * 0 = Disable 1 = Enable BIT 6 RxINT BIT 2 See Tables in MR0 description BIT (5:4) TxINT (1:0) See Table 13 BIT 3 FIFO Size 0 = 8 bytes 1 = 256 bytes BIT 2 BAUD RATE EXTENDED II 0 = NormaL 1 = Extend II BIT 1 Reserved Set to 0 BIT 0 BAUD RATE EXTENDED 1 0 = Normal 1 = Extend
MR0 A, MR0 B, and MR0 B[3:0] are reserved
*This bit control is duplicated at MR0[7]. MR0[7] Fixed length Watchdog Timer This bit controls the receiver watchdog timer. 0 = disable, 1 = enable. When enabled, the watch dog timer will generate a receiver interrupt if the receiver FIFO has not been accessed within 64 bit times of the receiver 1X clock. This is used to alert the control processor that data is in the RxFIFO that has not been read. This situation may occur when the byte count of the last part of a message is not large enough to generate an interrupt. MR0[6] - Bit 2 of receiver FIFO interrupt level. This bit along with Bit 6 of MR1 sets the fill level of the 8 byte FIFO that generates the receiver interrupt. MR0[6] and MR1[6] Note that this control is split between MR0 and MR1. This is for backward compatibility to the SC2692 and SCN2681. MR0[5:4] - Tx interrupt fill level.
Table 5. Transmitter FIFO Interrupt Fill Level MR0(3)=0
MR0[5:4] 00 01 10 11 Interrupt Condition 8 bytes empty (Tx EMPTY) 4 or more bytes empty 6 or more bytes empty 1 or more bytes empty (TxRDY)
Table 6. Transmitter FIFO Interrupt Fill Level MR0(3)=0
MR0[5:4] 00 01 10 11 Interrupt Condition 256 bytes empty (Tx EMPTY) 128 or more bytes empty 192 or more bytes empty 1 or more bytes empty (TxRDY)
Table 3. Receiver FIFO Interrupt Fill Level MR0(3)=0
MR0[6] MR1[6] 00 01 10 11 Interrupt Condition 1 or more bytes in FIFO (RxRDY) 3 or more bytes in FIFO 6 or more bytes in FIFO 8 bytes in FIFO (Rx FULL)
Table 4. Receiver FIFO Interrupt Fill Level MR0(3)=1
MR0[6] MR1[6] 00 01 10 11 Interrupt Condition 1 or more bytes in FIFO (RxRDY) 128 or more bytes in FIFO 192 or more bytes in FIFO 256 bytes in FIFO (Rx FULL)
For the transmitter these bits control the number of FIFO positions empty when the receiver will attempt to interrupt. After the reset the transmit FIFO has 8 bytes empty. It will then attempt to interrupt as soon as the transmitter is enabled. The default setting of the MR0 bits (00) condition the transmitter to attempt to interrupt only when it is completely empty. As soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request. MR0[3] - FIFO Size Selects between 8 or 256 byte FIFO structure MR0[2:0] - Legacy Baud Rate Group Selection These bits are used to select one of the six-baud rate groups. See Table 13 for the group organization.
For the receiver these bits control the number of FIFO positions filled when the receiver will attempt to interrupt. After the reset the receiver FIFO is empty. The default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it.
* 000 Normal mode * 001 Extended mode I * 100 Extended mode II
Other combinations of MR2[2:0] should not be used NOTE: MR0[3:0] are not used in channel B and should be set to 0.
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22
Philips Semiconductors
Objective specification
Dual UART
SC28L202
MR1 - Mode Register 1, A and B MR1 can be accessed directly at H'21" and H'29" in the Extended section of the address map, or by means of the "MR Pointers" at the 0x00 and 0x08 address pointers used by legacy code. Bit 7 RxRTS Control 0 = off 1 = on Bit 6 See Tables in MR0 description Bit 5 Error Mode 0 = Character 1 = Block (entry or exit) Bit 4:3 Parity Mode 00 = With Parity 01 = Force parity 10 = No parity 11 = Multi drop Special Mode Bit 2 Parity Type 0 = Even 1 = Odd Bit 1:0 Bits per Character 00 = 5 01 = 6 10 = 7 11 = 8
MR1[7] - Receiver Request to Send (hardware flow control) This bit controls the deactivation of the RTSN output (I/O2) by the receiver. The I/O2 output is asserted and negated by commands applied via the command register or through the setting of the OPR register bits. MR1[7] = 1 enables the receiver state machine to controls the sate of the I/O2 (where the RTSN function is assigned) to be automatically negated (driven high) upon receipt of a valid start bit if the receiver FIFO is 240 full or greater. (for 8-byte mode the FIFO full signal is used) RTSN is reasserted when the FIFO fill level falls below 240 filled FIFO positions. This constitutes a change from previous members of Philips (Signets)' UART families where the RTSN function triggered on FIFO full. This behavior caused problems with PC UARTs that could not stop transmission at the proper time. NOTE: When the FIFO is set to an 8-byte depth the RTSN signaling is triggered on position 8 of the FIFO The RTSN feature can be used to prevent overrun in the receiver, by using the RTSN output signal, to control the CTSN (see MR2(4) description) input of the transmitting device. It is not recommend to use the hardware flow control and the "in-band" (Xon/Xoff) flow control at the same time although the DUART hardware will allow it. To use the RTSN function: 1. Set MR1(7) to 1 2. Set I/O0 B or I/O1 B as appropriate to logical 0 3. Enable receiver MR1[6] - Receiver interrupt control bit 1. See description under MR0 [6]. (Writing to this register will reset the RxFIFO interrupt to the bit configuration of MR0 and MR1. Reading has no effect.) *** change in MR in legacy section - at MR0 also***
MR1 [5] - Error Mode Select and sub modes This bit selects the operating mode of the three FIFOed status bits (FE, PE, and received break). In the character mode, status is provided on a character by character basis; the status applies only to the character at the output of the FIFO. In the block mode, the status provided in the SR for these bits is the accumulation (logical OR) of the status for all characters coming to the output of the FIFO, since the last reset error command was issued. The Block Error mode has two-sub mode. These modes are controlled by the command register. The error is "accumulated" (as described above) at either the entry of the data in to the FIFO or on the exit (read of the FIFO). Of the two the setting of the error on the entry of the data into the FIFO gives the earliest warning of error data. MR1[4:3] - Parity Mode Select If 'with parity' or 'force parity' is selected, a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data. MR1[4:3] = 11 selects the channel to operate in the special wake up mode. MR1[2] - Parity Type Select This bit sets the parity type (odd or even) if the 'with parity' mode is programmed by MR1[4:3], and the polarity of the forced parity bit if the 'force parity' mode is programmed it has no effect if the 'no parity' mode is programmed. In the special 'wake up' mode, it selects the polarity of the A/D bit. The parity bit is used to an address or data byte in the 'wake up' mode. MR1[1:0] - Bits per Character Select This field selects the number of data bits per character to be transmitted and received. This number does not include the start, parity, or stop bits.
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23
Philips Semiconductors
Objective specification
Dual UART
SC28L202
MR2 - Mode Register 2, A and B MR2 can be accessed directly at 0x22 and 0x2A in the Extended section of the address map, or by means of the "MR Pointers" at the 0x00 and 0x08 address pointers used by legacy code. The MR2 register provides basic channel setup control that may need more frequent updating. Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MR2 A CHANNEL MODE Tx CONTROLS CTS STOP BIT LENGTH MR2 B RTS ENABLE Tx NOTE: Add 0.5 to binary codes 0 - 7 for 5 bit character lengths. 00 = Normal 01 = Auto-Echo 10 = Local loop 11 = Remote loop 0 = No 1 = Yes 0 = No 1 = Yes 0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813 1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875 2 = 0.688 6 = 0.938 A = 1.688 E = 1.938 3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
NOTE: 1. Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char. MR2[7:6] - Mode Select The DUART can operate in one of four modes: Normal, Automatic Echo, Local Loop Back and Remote Loop Back MR2[7:6] = b'00 Normal Mode Normal and default mode The transmitter and receiver operating independently. MR2[7:6] = b'01 Automatic Echo Places the channel in the automatic echo mode, which automatically retransmits the received data. The following conditions are true while in automatic echo mode: * Received data is re-clocked and re-transmitted on the TxD output.
* A received break is echoed as received until the next valid start bit
is detected. MR2[5] Transmitter Request to Send Control This bit controls the deactivation of the RTSN output (I/O2) by the transmitter. This output is manually asserted and negated by appropriate commands issued via the command register. MR2 [5] = 1 negates (drives to logical 1) RTSN automatically one bit time after the characters in the transmit shift register and in the TxFIFO (if any) are completely transmitted (includes the programmed number of stop bits if the transmitter is not enabled). This feature can be used to automatically terminate the transmission of a message as follows: * Program auto reset mode: MR2[5]= 1.
* The receiver clock is used for the transmitted data. * The receiver must be enabled, but the transmitter need not be * The TxRDY and Tx Idle status bits are inactive. * The received parity is checked, but is not regenerated for
enabled.
* Enable transmitter. * Assert RTSN via command. * Send message. * Verify the next to last character of the message is being sent by *
* Character framing is checked, but the stop bits are retransmitted * *
as received. Rx data is sent to RxFIFO A received break is echoed as received until the next valid start bit is detected. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled.
transmission, i.e., transmitted parity bit is as received.
waiting until transmitter ready is asserted. Disable transmitter after the last character is loaded into the TxFIFO. The last character will be transmitted and RTSN will be reset one bit time after the last stop bit.
* The transmitter output is internally connected to the receiver input. * The transmitter's 1X clock is used for the receiver. * The TxD output is held high. * The RxD input is ignored. * The transmitter must be enabled, but the receiver need not be * CPU to transmitter and receiver communications continue
normally. MR2 [7:6] = b'11 Selects the Remote Loop back diagnostic mode. In this mode: enabled.
MR2[7:6] = b'10 selects local loop back diagnostic mode. In this mode:
NOTE: when the transmitter controls the RTSN pin the meaning of the pin is COMPLETELY changed. It has nothing to do with the normal RTSN/CTSN "handshaking". It is usually used to mean, "end of message" and to "turn the line around" in simplex communications. From a practical point of view the simultaneous use of Tx control of RTSN and Rx control is mutually exclusive. However if this is programmed the DUART performs as required. MR2[4] - Clear to Send Control The state of this bit determines if the CTSN input (I/O0) controls the operation of the transmitter. If this bit is 0, CTSN has no effect on the transmitter. If this bit is a 1, the transmitter checks the state of CTSN each time it is ready to begin sending a character. If it is asserted (low), the character is transmitted. If it is negated (high), the TxD output remains in the marking state and the transmission is delayed until CTSN goes low. Changes in CTSN, while a character is being transmitted, do not affect the transmission of that character. This feature can be used to prevent overrun of a remote receiver. MR2[3:0] - Stop Bit Length Select This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of 9/16 through 2 bits can be programmed. In all cases, the receiver only checks for a mark condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled). If an external 1X clock is used for the transmitter, MR2[1] = 0 selects one stop bit and MR2[1] = 1 selects two stop bits to be transmitted.
* Received data is re-clocked and re-transmitted on the TxD output. * The receiver 1X clock is used for the transmitted data. * Received data is not sent to the local CPU, and the error status * The received parity is not checked and is not regenerated for * The receiver must be enabled, but the transmitter need not be * Character framing is not checked, and the stop bits are
retransmitted as received. 2000 Feb 10 24 enabled. transmission, i.e., the transmitted parity bit is as received. conditions are inactive.
Philips Semiconductors
Objective specification
Dual UART
SC28L202
MR3 - Mode Register 3, A and B Bit 7 Xon/Xoff 1 transparency 0 = flow control characters received are loaded onto the RxFIFO 1 = flow control characters received are not loaded onto the RxFIFO Bit 6 Address Recognition 1 transparency 0 = Address characters received are loaded to RxFIFO 1 = Address characters received are not loaded onto the RxFIFO Bit 5:4 Reserved Bit 3:2 In-band flow control mode 00 = host mode, only the host CPU may initiate flow control actions through the CR 01 = Auto Transmitter flow control 10 = Auto Receiver flow control 11 = Auto Rx and Tx flow control Bit 1:0 Address Recognition control 00 = Default 01 = Auto wake 10 = Auto doze 11 = Auto wake and auto doze
NOTE: 1. If these bits are not 0 the characters will be stripped regardless of bits (3:2) or (1:0) MR3[7 & 6] Xon/Xoff Character Stripping Control the handling of recognized Xon/Xoff or Address characters. If set, the character codes are placed on the RxFIFO along with their status bits just as ordinary characters are. If the character is not loaded onto the RxFIFO, its received status will be lost unless the receiver is operating in the block error mode, see MR1[5] and the general discussion on receiver error handling. Interrupt processing is not effected by the setting of these bits. See Character recognition section. MR3[5:4] Reserved MR3[3:2] Xon/Xoff Processing Control the Xon/Xoff processing logic. Auto Transmitter flow control allows the gating of Transmitter activity by Xon/Xoff characters received by the Channel's receiver. Auto Receiver flow control causes the Transmitter to emit an Xoff character when the RxFIFO has loaded to a depth of 240 characters. Draining the RxFIFO to a level of 128 or less causes the Transmitter to emit a Xon character. All transmissions require no host involvement. A setting other than b'00 in this field precludes the use of the command register to transmit Xon/Xoff characters. NOTE: Interrupt generation in Xon/Xoff processing is controlled by the IMR (Interrupt Mask Register) of the individual channels. The interrupt may be cleared by a read of the XISR, the Xon/Xoff Interrupt Status Register. Receipt of a flow control character will always generate an interrupt if the IMR is so programmed. The MR0[3:2] bits have effect on the automatic aspects of flow control only, not the interrupt generation. MR3[1:0] Address Recognition This field controls the operation of the Address recognition logic. If the device is not operating in the special or "wake-up" mode, this hardware may be used as a general-purpose character detector by choosing any combination except b'00. Interrupt generation is controlled by the channel IMR. The interrupt may be cleared by a read of the XISR, the Xon/Xoff Interrupt Status Register. See further description in the section on the Wake Up mode.
2000 Feb 10
25
Philips Semiconductors
Objective specification
Dual UART
SC28L202
RxCSR - Receiver Clock Select Register A and B TxCSR Transmitter Clock Select Register A and B Both registers consist of single 6-bit field that selects the clock source for the receiver and transmitter respectively. During a read the unused bits in this register read b'000. The "BRG" baud rates (fixed BRG rates) shown in the table below are based on the Sclk crystal frequency of 14.7456 MHz. The baud rates shown below will vary as the Sclk crystal clock varies. For example, if the Sclk rate is changed to 7.3728 MHz all the rates below will reduce by 1/2. Bit 7 Reserved Rx and Tx Clock Select Table NOTE: Sclk maximum rate is 50 MHz. Data clock rates will follow exactly the ratio of the X1/Sclk to 14.7654 MHz Tx A Clock Select Code 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 Tx A Clock Select Code Clock selection, Sclk = 14.7456 MHz BRG - 50 BRG - 110 BRG - 134.5 BRG - 200 BRG - 300 BRG - 600 BRG - 1200 BRG - 1050 BRG - 2400 BRG - 4800 BRG - 7200 BRG - 9600 BRG - 38.4K Timer 0 I/O3 A transmitter - 16x External * I/O3 A transmitter - 1x External * Clock selection, Sclk = 14.7456 MHz Tx A Clock Select Code 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 Tx A Clock Select Code 11 0000 to 11 1101 11 1110 11 1111 Clock selection, Sclk = 14.7456 MHz BRG - 75 BRG - 150 BRG - 450 BRG - 1800 BRG - 2000 BRG - 14.4K BRG - 19.2K BRG - 28.8K BRG - 57.6K BRG - 115.2K BRG - 230.4K BRG - 460.8K BRG - 921.6K Timer 1 PBRG 0 Midi rate 31.25 KHz 1.66% error Clock selection, Sclk = 14.7456 MHz Reserved PBRG 1 Reserved Bit 6 Reserved Bits 5:0 Transmitter/Receiver Clock select code, See Clock Multiplex Table below
This field selects the baud rate clock for the Channel A transmitter. * External clock Pin and external clock mode assignment. Tx/Rx CSR x [5:0] 001110 001111 RxC Channel A I/O4 A 16x I/O4 A 1X TxC Channel B I/O5 A 16x I/O5 A 1X RxC channel B I/O6 A 16x I/O6 A 1X
2000 Feb 10
26
Philips Semiconductors
Objective specification
Dual UART
SC28L202
CRx - Command Register Extension, A and B CR is used to write commands to the DUART. Bit 7 Lock Tx and Rx Enables 0 = lock Rx & Tx state 1 = Change Rx & Tx state Bit 6 Enable Tx 0 = disable 1 = enable Bit 5 Enable Rx 0 = disable 1 = enable Bit 4:0 Command Register codes. (See Command Register Table)
CR[7] - Lock Tx and Rx enables. If reset, the transmitter and receiver enable bits, CR[6:5] are not significant. The enabled/disabled state of a receiver or transmitter can be changed only if this bit is a "1" during the time of the write to the command register. WRITES TO THE LOWER 5 BITS OF THE CR WOULD USUALLY HAVE CR[7] AT "0" to maintain the condition of the receiver and transmitter. The bit provides a mechanism for writing commands to a channel, via CR[4:0], without the necessity of keeping track of or reading the current enable status of the receiver and transmitter. CR[6] - Enable Transmitter A one written to this bit enables operation of the transmitter. The TxRDY status bit will be asserted. When disabled by writing a zero to this bit, the command terminates transmitter operation and resets the TxRDY and Tx Idle status bits returning the transmitter to its idle state . However, if a character is being transmitted or if characters are loaded in the TxFIFO when the transmitter is disabled, the transmission of the all character(s) is completed before assuming the inactive state. CR[5] - Enable Receiver A one written to this bit enables operation of the receiver. The receiver immediately begins the search for and the verification the start bit. If a zero is written, this command terminates operation of the receiver immediately - a character being received will be lost. The command has no effect on the receiver status bits or any other control registers. The data in the RxFIFO will be retained and may be read. If the receiver is re-enabled subsequent data will be appended to that already in the RxFIFO. If the special wake-up mode is programmed, the receiver operates even if it is disabled (see Wake-up Mode). CR[4:0] - Miscellaneous Commands (See Table below) The encoded value of this field can be used to specify a single command as follows:
* 00110 Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be delayed up to two bit times. If the transmitter is active and the TxFIFO is empty then the break begins when transmission of the current character is completed. If there are characters in the TxFIFO, the start of break is delayed until all characters presently in the TxFIFO and any subsequent characters loaded have been transmitted. (Tx Idle must be true before break begins).
* 00111 Stop break. The TxD line will go high (marking) within two
bit times. TxD will remain high for one bit time before the next character is transmitted.
The transmitter must be enabled to start a break.
* 01000 Assert RTSN. Causes the RTSN output to be asserted
(low).
* 01001 Negate RTSN. Causes the RTSN output to be negated
(high). NOTE: The two commands above actually reset and set, respectively, the I/O0 B (Channel A) or I/O1 B (Channel B) pin associated with the OPR register. (See SOPR and ROPR registers I/O pin control.
* 01010 Set C/T Receiver time out mode on * 01011 Set MR Pointer to 0 * 01100 Set C/T Receiver time out mode off * 01101 Block error status accumulation on FIFO entry. Allows the
"received break", "framing error" and "parity error" bits to be set as the received character is loaded to the RxFIFO. (normally these bits are set on reading of the data from the RxFIFO) Setting this mode can give information about error data up to 256 bytes earlier than the normal mode. However it clouds the ability to know precisely which byte(s) are in error.
* 00000 No command. * 00001 Reserved * 00010 Reset receiver. Immediately resets the receiver as if
hardware reset had been applied. The receiver is reset and the FIFO pointer is reset to the first location effectively discarding all unread characters in the FIFO.
* 01110 Power Down Mode On * 01111 Disable Power Down Mode * 10000 Transmit an Xon Character * 10001 Transmit an Xoff Character * 10010 C/T start sets the counter timer to the value of the
counter/timer preset register and starts the counter.
* 00011 Reset transmitter. Immediately resets the transmitter as if a
hardware reset had been applied. The transmitter is reset and the FIFO pointer is reset to the first location effectively discarding all untransmitted characters in the FIFO.
* 10011 C/T stop Effectively stops the counter/timer, captures the
last count value and resets the counter ready status bit in the ISR
* 00100 Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register (SR[7:4]). It is used in either character or block mode. In block mode it would normally be used after the block is read.
* 10100 Reserved * 10101 Reserved. * 10110 Transmitter resume command (This command is not active
in "Auto-Transmit mode"). A command to cancel a previous Host Xoff command. Upon receipt, the channel's transmitter will transfer a character, if any, from the TxFIFO and begin transmission.
* 00101 Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be cleared to zero. 2000 Feb 10 27
Philips Semiconductors
Objective specification
Dual UART
SC28L202
* 10111 Host Xoff (or transmitter pause) command (CRTXoff). This
command allows tight host CPU control of the flow control of the channel transmitter. When interrupted for receipt of a Xoff character by the receiver, the host may stop transmission of further characters by the channel transmitter by issuing the Host Xoff command. Any character that has been transferred to the TxD shift register will complete its transmission, including the stop bit before the transmitter pauses. Even though the transmitter is paused it is still able to send Xon/Xoff by the request of its associated receiver.
* 11001 Reserved * 11010 Reserved * 11011 Reset Address Recognition Status. This command clears
the interrupt status that was set when an address character was recognized by a disabled receiver operating in the special mode.
* 11100 Reserved * 11101 Block error status accumulates on FIFO read (Default
State)
* 11000 Cancel Host transmit flow control command. Issuing this
command will cancel a previous command to transmit a flow control character if the flow control character is not yet loaded into the TxD Shift Register. If there is no character waiting for transmission or if its transmission has already begun, then this command has no effect and the character will be sent.
* 11110 Reset to "C92" Register Set * 11111 Reserved for channel B, for channel A: executes a chip
wide reset. Executing this command in channel a is equivalent to a hardware reset with the RESET(N) pin. Executing in channel B has no effect.
COMMAND REGISTER EXTENSION TABLE A and B Commands 0x0F, 0x0F, 0xFF (marked with * ) are global and exist only in channel A's register space. Channel Command Code CR[4:0] 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 Channel Command Description NOP Set MR pointer to 1 Reset Receiver Reset Transmitter Reset Error Status Reset Break Change Interrupt Begin Transmit Break End Transmit Break Assert RTSN (I/O0 B or I/O1 B) Negate RTSN (I/O0 B or I/O1 B) Set C/T Receiver time-out mode on Set MR pointer to 0 Set C/T Receiver time-out mode off Block Error Status on RxFIFO load * Power Down Mode On * Disable Power Down Mode Channel Command Code CR[4:0] 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111 Channel Command Description Transmit Xon Transmit Xoff Start C/T Stop C/T Reserved Reserved Transmitter Resume Command (CRXoffRe) Host Xoff Command (CRTXoff) Cancel Transmit X Char Command (CRTX) Reserved Reserved Reset Address Recognition Status Reserved Block Error Status on RxFIFO Read Reserved * Reset Device as a Hardware reset. Reserved in channel B*
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
SR - Channel Status Register A and B Bit 7 Received Break 0 = No 1 = Yes Bit 6 Framing Error 0 = No 1 = Yes Bit 5 Parity Error 0 = No 1 = Yes Bit 4 Overrun Error 0 = No 1 = Yes Bit 3 Tx Idle 0 = No 1 = Yes Bit 2 TxRDY 0 = No 1 = Yes Bit 1 RxFULL 0 = No 1 = Yes Bit 0 RxRDY 0 = No 1 = Yes
SR[7] - Received Break This bit indicates that an all zero character (including parity, if used) of the programmed length has been received with a stop bit at a logical zero. A single FIFO position is loaded with 0x00 when a break is received; further entries to the FIFO are inhibited until the RxD line returns to the marking state for at least one half bit time (two successive edges of the internal or external 1x clock). When this bit is set, the change in break bit in the ISR (ISR [2]) is set. ISR[2] is also set when the end of the break condition, as defined above, is detected. The break detect circuitry is capable of detecting breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must last until the end of the next character in order for it to be detected. SR[6] - Framing Error (FE) This bit indicates that a stop bit was not detected when an otherwise non-zeros data character (including parity, if enabled) was received. The stop bit check is made in the middle of the first stop bit position. SR[5] - Parity Error (PE) This bit is set when the 'with parity' or 'force parity' mode is programmed and the corresponding character in the FIFO was received with incorrect parity. In the special 'wake up mode', the parity error bit stores the received A/D bit. SR[4] - Overrun Error (OE) This bit, when set, indicates that one or more characters in the received data stream have been lost. It is set upon receipt of the start bit of a new character when the RxFIFO is full and a character is already in the receive shift register (257 valid characters in the receiver) waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. This bit is cleared by a reset error status command. SR [3] - Transmitter Idle (Tx Idle) This bit is set when the transmitter underruns, i.e., both the TxFIFO and the transmit shift register are empty. It is set after transmission
of the last stop bit of a character, if no character is in the TxFIFO awaiting transmission. It is negated when the TxFIFO is loaded by the CPU, or when the transmitter is disabled or reset. This bit is concerned with the transmitter transmitting data and it essentially shows " transmitter underrun". If, while it is underrun it is commanded to send an X on/Xoff character it will remain at the zero state. If it is underrun and while sending an Xon/Xoff character the TxFIFO is loaded then the bit will go low. SR[2] - Transmitter Ready (TxRDY) This bit, when set, indicates that the TxFIFO is ready to be loaded with at least one more character. This bit is cleared when the TxFIFO is full or is above its interrupt threshold level set in the MR registers or TxFIFO interrupt Fill Level register (TxFIL). Characters loaded in the TxFIFO while the transmitter is disabled will not be transmitted. SR[1] - RxFIFO Full (RxFULL) This bit is set when a character is transferred from the receive shift register to the receive FIFO and the transfer causes the FIFO to become full, i.e., all 256 RxFIFO positions are occupied. It is reset when the CPU reads the RxFIFO and that read leaves one or more empty byte position(s). If a character is waiting in the receive shift register because the RxFIFO is full, RxFULL is not reset until the second read of the RxFIFO since the waiting character is immediately loaded to the RxFIFO. SR[0] - Receiver Ready (RxRDY) This bit indicates that a character has been received and is waiting in the RxFIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the RxFIFO and reset when the CPU reads the RxFIFO, and no more characters are in the RxFIFO.
2000 Feb 10
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
ISR - Interrupt Status Register A and B Bit 7 Bit 6 Bit 5 I/O Port Receiver Address Change Watch-dog recognition event of Time-out state
Bit 4 Xon/off event
Bit 3 C/T Ready
Bit 2 Break Change Of state
Bit 1 RxINT Receiver entered the arbitration process.
Bit 0 TxINT Transmitter entered the arbitration process.
This register provides the status of all potential interrupt sources for a UART channel. When generating an interrupt arbitration value, the contents of this register are masked by the interrupt mask register (IMR). If a bit in the ISR is a '1' and the corresponding bit in the IMR is also a `1'; interrupt arbitration for this source will begin. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR can have no affect on the IRQN output. Note that the IMR may or may not mask the reading of the ISR as determined by GCCR[06]. If GCCR[0] is cleared, the reset and power on default, the ISR is read without modification. If GCCR[0] is set, the read of the ISR gives a value of the ISR ANDed with the IMR. ISR[7] - Input Change of State. This bit is set when a change of state occurs at the I/O1 or I/O0 input pins. It is reset when the CPU reads the Input Port Register, IPR. ISR[6] Fixed Watchdog Time-out. This bit is set when the receiver's watchdog timer has counted more than 64 bit times since the last RxFIFO event. RxFIFO events are a read of the RxFIFO or GRxFIFO, or the load of a received character into the FIFO. The interrupt will be cleared automatically when the RxFIFO or GRxFIFO is read. The receiver watch-dog timer is included to allow detection of the very last characters of a received message that may be waiting in the RxFIFO, but are too few in number to successfully initiate an interrupt. Refer to the watchdog timer description for details of how the interrupt system works after a watchdog time-out. ISR[5] - Address Recognition Status Change. This bit is set when a change in receiver state has occurred due to an Address character being received from an external source and matches the reference address in ARCR. The bit and interrupt is negated by a write to the CR with command x11011, Reset Address Recognition Status. ISR[4] - Xon/Xoff Status Change. This bit is set when a Xon/Xoff character being received from an external source. The bit is negated by a read of the channel Xon/Xoff Interrupt Status Register, XISR. ISR[3] - Counter Timer Status The C/T has timed out or the count passed through 0. This bit is cleared by issuing the "stop C/T " command. ISR[2] - Change in Channel Break Status. This bit, when set, indicates that the receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a reset break change interrupt command via the CR.
ISR[1] - RxINT. (Also Rx DMA hand shake at I/O pins) The general function of this bit is to indicate that the RxFIFO has data available and that it has entered the arbitration process. The particular meaning of this bit is programmed by RxFIL register. If programmed as receiver ready (MR2[3:2] = 00), it indicates that at least one character has been received and is waiting in the RxFIFO to be read by the host CPU. It is set when the character is transferred from the receive shift register to the RxFIFO and reset when the CPU reads the last character from the RxFIFO. If RxFIL is programmed as FIFO full, ISR[1] is set when a character is transferred from the receive holding register to the RxFIFO and the transfer causes the RxFIFO to become full, i.e. all 256 FIFO positions are occupied. It is reset whenever RxFIFO is not full. If there is a character waiting in the receive shift register because the FIFO is full, the bit is set again when the waiting character is transferred into the FIFO. The other two conditions of these bits, 3/4 and half full operate in a similar manner. The ISR[1] bit is set when the RxFIFO fill level meets or exceeds the value; it is reset when the fill level is less. See the description of the MR2 register. NOTE: This bit must be at a one (1) for the receiver to enter the arbitration process. It is the fact that this bit is zero (0) when the RxFIFO is empty that stops an empty FIFO from entering the interrupt arbitration. Also note that the meaning if this bit is not quite the same as the similar bit in the status register (SR). ISR[0] - TxINT. (Also Tx DMA hand shake at I/O pins) The general function of this bit is to indicate that the TxFIFO has an at least one empty space for data. The particular meaning of the bit is controlled by MR0 [5:4] indicates the TxFIFO may be loaded with one or more characters. If MR0[5:4] = 00 (the default condition) this bit will not set until the TxFIFO is empty - 256 bytes available. If the fill level of the TxFIFO is below the trigger level programmed by the TxINT field of the Mode Register 0, this bit will be set. A one in this position indicates that at least one character can be sent to the TxFIFO. It is turned off as the TxFIFO is filled above the level programmed by MR0[5:4. This bit turns on as the FIFO empties. (Note that the RxFIFO bit turns on as the FIFO fills.) This often a point of confusion in programming interrupt functions for the receiver and transmitter FIFOs. NOTE: This bit must be at a one (1) for the transmitter to enter the arbitration process. It is the fact that this bit is zero (0) when the TxFIFO is full that stops a full TxFIFO from entering the interrupt arbitration. Also note that the meaning if this bit is not quite the same as the similar bit in the status register (SR).
2000 Feb 10
30
Philips Semiconductors
Objective specification
Dual UART
SC28L202
IMR - Interrupt Mask Register A and B Bit 7 I/O Port Change of state Bit 6 Rx Watch-dog Time-out Bit 5 Address recognition event Bit 4 Xon/off event Bit 3 C/T Ready Bit 2 Break Change Of State Bit 1 RxRDY interrupt Bit 0 TxRDY interrupt
The programming of this register selects which bits in the ISR cause an interrupt output. If a bit in the ISR is a '1' and the corresponding bit in the IMR is a '1', the interrupt source is presented to the internal interrupt arbitration circuits, eventually resulting in the IRQN output being asserted (low). If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no affect on the IRQN output. IMR[7] COS enable Allows a change of state in the inputs equipped with input change detectors to cause an interrupt. IMR[6] Fixed Watchdog Enable Controls the generation of an interrupt watchdog timer event. If set, a count of 64 idle bit times in the receiver will begin interrupt arbitration. IMR[5] Address recognition enable Enables the generation of an interrupt in response to changes in the Address Recognition circuitry of the Special Mode (multi-drop or wake-up mode). RxFIFO - Receiver FIFO, A and B Bit[10] Bit[9] These bits are sent to the status register Break Framing Received Status Error Status Bit[8] Parity Error Status
IMR[4] Xon/Xoff Enable Enables the generation of an interrupt in response to recognition of an in-band flow control character. IMR[3] Counter/Timer Enable Enable the C/T interrupt when the C/T reaches 0 count.[2] Enables the generation of an interrupt when a Break condition has been detected by the channel receiver. IMR[1] Receiver (Rx) Enable Enables the generation of an interrupt when servicing for the RxFIFO is desired. IMR[0] Transmitter (Tx) Enable Enables the generation of an interrupt when servicing for the TxFIFO is desired.
Bits [7:0] This the data byte sent to the data bus or RxFIFO read 8 data bits MSBs =0 for 7,6,5 bit data The foregoing applies to the "character error" mode of status reporting. See MR1[5] and "RxFIFO Status" descriptions for "block error" status reporting. Briefly, "Block Error" gives the accumulated error of all bytes received by the RxFIFO since the last "Reset Error" command was issued. (CR = 0x04)
The FIFO for the receiver is 11 bits wide and 256 "words" deep. The status of each byte received is stored with that byte and is moved along with the byte as the characters are read from the FIFO. The upper three bits are presented in the STATUS register and they change in the status register each time a data byte is read from the FIFO. Therefor the status register should be read BEFORE the byte is read from the RxFIFO if one wishes to ascertain the quality of the byte TxFIFO - Transmitter FIFO, A and B Bits 7:0 8 data bits. MSBs set to 0 for 7, 6, 5 bit data
The FIFO for the transmitter is 8 bits wide by 256 bytes deep. For character lengths less than 8 bits the upper bits will be ignored by the transmitter state machine and thus are effectively discarded. RxFIL - Receiver FIFO Interrupt Level, A and B Bits 7:0 Any one of 256 FIFO fill positions The position in the Rx FIFO that causes the receiver will enter the interrupt arbitration process. This register is used to offset the effect of the arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also "equalize" interrupt latency and allow for larger aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1. RxFL - Receiver FIFO Fill Level Register Bits 7:0 Channel byte count code ** (1) = implied `1' 00000001 = 1 00000010 = 2 to 11111111 = 255 **(1)00000000 = 256 if RxRDY status bit is set. The number of bytes filled in the receiver FIFO 2000 Feb 10 31
Philips Semiconductors
Objective specification
Dual UART
SC28L202
TxFIL - Transmitter FIFO Interrupt Level A and B Bits 7:0 Any one of 256 FIFO empty positions The position in the Tx FIFO that caused the transmitter will enter the interrupt arbitration process. This register is used to offset the effect of the arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also "equalize" interrupt latency and allow for larger aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1. TxEL - Transmitter FIFO Empty Level Register Bits 7:0 Channel byte count code ** (1) = implied `1' 00000001 = 1 00000010 = 2 to 11111111 = 255 **(1)00000000 = 256 if TxRDY status bit is set. The number of empty bytes in the Transmitter FIFO
Registers for Character Recognition
XonCR - Xon/Xoff Character Register A and B Bits 7:0 8 Bits of the Xon Character Recognition (Resets to 0x11) An 8-bit character register that contains the compare value for a Xon character. XoffCR - Xoff Character Register A and B Bits 7:0 8 Bits of the Xoff Character Recognition (Resets to 0x13) An 8-bit character register that contains the compare value for a Xoff character. ARCR - Address Recognition Character Register A and B Bits 7:0 8 Bits of the Multi-Drop Address Character Recognition (Resets to 0x00) An 8 bit character register that contains the compare value for the wake-up address character
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
XISR - Xon-Xoff Interrupt Status Register A and B (Reading this register clears XISR(7:4)) Bits 7:6 Received X Character Status 00 = none 01 = Xoff received 10 = Xon received 11 = both received Bits 5:4 Automatic X Character transmission status 00 = none 01 = Xon transmitted 10 = Xoff transmitted 11 = Both transmitted Bits 3:2 TxD flow status 00 = normal transmission 01 = TxD halt pending 10 = re - enabled 11 = flow halted Bits 1:0 TxD character status 00 = normal TxD data 01 = Idle wait for FIFO data 10 = Xoff in pending 11 = Xon in pending
XISR[7:6] Received X Character Status. This field can be read to determine if the receiver has encountered a Xon or Xoff character in the incoming data stream. These bits are maintained until a read of the XISR. The field is updated by X character reception regardless of the state of MR3(7) and MR3(3:2) or IMR(4). The field can therefore be used as a character detector for the bit patterns stored in the Xon and Xoff Character Registers. XISR[5:4] Automatic transmission Status. This field indicates the last flow control character sent in the Auto Receiver flow control mode. If Auto Receiver mode has not been enabled, this field will always read b'00. It will likewise reset to b'00 if MR0(3) is reset. If the Auto Receiver mode is exited while this field reads b'10, it is the user's responsibility to transmit a Xon, when appropriate. XISR[3:2] TxD Condition of the automatic flow control status. This field tracks the transmitter's flow status as follows:
* 10 - re-enabled. The transmitter had been halted and has been
restarted. It is sending (or is prepared to send) data characters.
* 11 - The transmitter is stopped due to an Xoff character being
received from its associated receiver. The transmitter is "flow controlled". XISR[1:0] TxD X character Status. This field allows determination of the type of character being transmitted. It will always be b'00 if none of the automatic X character controls of MR3[3:2] is enabled.
After a read of the XISR, it will return to "normal" status.
* 01 - The channel is waiting for a data character to transfer from
the TxFIFO. This condition will only occur for a bit time after a Xon or Xoff character transmission unless the TxFIFO is empty.
* 00 - normal transmission. Transmitter is not affected by Xon or
Xoff.
* 10 - A command to send an Xoff character is pending. * 11 - A command to send an Xon character is pending.
Conditions b'10 and b'11 will not exist for more than a character time.
* 01 - TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b'11.
WCXER Watch Dog, Character, Address and X Enable Register - A and B Bit 7 Watch dog * 1 = disable Wd 0 = no action Bit 6 1 = enable Wd 0 = no action Bit 5 Bit 4 Address recognition 1 = disable Ar 1 = enable Ar 0 = no action 0 = no action BIT 3 BIT 2 Xon recognition 1 = disable 1 = enable Xon Xon 0 = no action 0 = no action BIT 1 BIT 0 Xoff Recognition 1 = disable 1 = enable Xoff Xoff 0 = no action 0 = no action
This register enables the UART's Character Recognition, Address Recognition and Receiver watchdog timer. If both enable and disable are active a disable results. This register is used to enable the general-purpose character recognition feature WITHOUT
causing any Xon/Xoff or wakeup mode activities to occur. The recognition event is reported in the ISR register. * This bit control is duplicated at MR0[7].
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
Programmable Counters, Timers and Baud Rate generators
PBRGPU - Programmable BRG Timer Reload Registers, Upper 0 and 1 Bits 7:0 8 MSBs of the BRG Timer divisor. This is the upper byte of the 16-bit value used by the BRG timer in generating a baud rate clock PBRGPL - Programmable BRG Timer Reload Registers, Lower 0 and 1 Bits 7:0 8 LSB of the BRG Timer divisor. This is the lower byte of the 16-bit value used by the BRG timer in generating a baud rate clock. CTCS 0 and 1 - Counter Timer clock source NOTE: Writing to this register removes the control established in the counter/timer portion of the ACR in the default register map Bit 7:6 Reserved Bit 5:4 Mode control 00 - Selects Counter Mode. Generates a timing edge 01 - Selects Timer Mode. Generates a square wave 10 - Reserved 11 - Selects Timer Pulse Mode. Generates periodic pulses twice the frequency as in Timer Mode. Pulse width is one cycle of the clock as it is delivered to the C/T. (i.e. after any prescale) CTVU - Counter Timer Value Registers, Upper 0 and 1 Bits 7:0 8 MSBs of the Counter timer preset value Reading this register gives the value of the upper 8 bits of the counter timer CTVL - Counter timer Value Registers, Lower 0 and 1 Bits 7:0 8 LSB of the Counter timer preset value Reading this register gives the value of the upper 8 bits of the counter timer NOTE: The counter timer should be stopped before reading. Usually the clock of the counter timer is not synchronized with the read of the C/T. It is therefore possible to capture changing data during the read. Depending on the clock speed with respect to the read cycle PBRGCS - Programmable BRG Clock Source Bit 7 PBRG 1, Register control 0 = Resets PBRG 1 and holds it stopped 1 = Allows PBRG 1 to run. Bit 6:4 PBRG 1, Clock selection 000 = Sclk 001 = Sclk / 2 010 = Sclk/ 16 011 = Sclk / 32 100 = Sclk / 64 101 = Sclk / 128 110 = I/O4 A 111 = Reserved Bit 3 PBRG 0, Register control 0 = Resets PBRG 0 and holds it stopped. 1 = Allows PBRG 0 to run. Bit 2:0 PBRG 0, Clock selection 000 = Sclk 001 = Sclk / 2 010 = Sclk / 16 011 = Sclk / 32 100 = Sclk / 64 101 = Sclk / 128 110 = I/O3 A 111 = Reserved Bit 3:0 Clock selection 0000 External I/O2 A (for CT 0), I/O7 A (for CT 1) 0001 External I/O2 A/16 (for CT 0), I/O7 A/16 (for CT 1) 0010 Sclk 0011 Sclk / 2 0100 Sclk / 16 0101 Sclk / 32 0110 Sclk / 64 0111 Sclk / 128 TxC1X A TxC1X B 1010, 1011 Reserved 1100 Rx Character Count (Ch A) Clock is RxFIFO A load pulse 1101 Rx Character Count (Ch B) Clock is RxFIFO B load pulse 1110, 1111 Reserved
this could be made worse or completely eliminated. If the Stop counter command is issued and following that the C/T is read there will be no uncertainty go its value. If it is necessary to read the C/T "on the fly" then reading it twice and comparing the values will correct the problem. The double read will not be effective if the counter timer clock is faster than a read cycle.
Start/Stop control and clock select register for the two BRG counters. The clock selection is for the input to the counters. It is that clock divided by the number represented by the PBRGPU and PBRGPL the will be used as the 16x clock for the receivers and transmitters. When the BRG timer Clock is selected for the
receiver(s) or transmitter(s) the receivers and transmitters will consider it as a 16x clock and further device it by 16. In other words the receivers and transmitters will always be in the 16x ode of operation when the internal BRG timer is selected for their clock.
2000 Feb 10
34
Philips Semiconductors
Objective specification
Dual UART
SC28L202
CTPU Counter Timer Preset Upper 0 and 1 CTPU Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 The lower eight (8) bits for the 16 bit counter timer preset register BIT 2 BIT 1 BIT 0
CTPL Counter -Timer Preset Low 0 and 1 CTPL Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 The Upper eight (8) bits for the 16 bit counter timer preset register BIT 2 BIT 1 BIT 0
The CTPU and CTPL hold the eight MSBs and eight LSBs, respectively, of the value to be used by the counter/timer in either the counter or timer modes of operation. The minimum value that may be loaded into the CTPU/CTPL registers is H`0000'. Note that these registers are write-only and cannot be read by the CPU. In the timer mode, the C/T generates a square wave whose period is twice the value (in C/T clock periods) of the CTPU and CTPL. The waveform so generated is often used for a data clock. The formula for calculating the divisor n to load to the CTPU and CTPL for a particular 1X data clock is shown below. NOTE: The 2 in the denominator is for the Square wave generation. For the Pulse mode change the 2 to a 1. n+ Clockinputfrequency 16 (Baud rate desired))
output remains high until terminal count is reached; at which time it goes low. The output returns to the High State and ISR [3] is cleared when the counter is stopped by a stop counter command. The CPU may change the values of CTPU and CTPL at any time, but the new count becomes effective only on the next start counter commands. If new values have not been loaded, the previous count values are preserved and used for the next count cycle In the counter mode, the current value of the upper and lower 8 bits of the counter (CTPU, CTPL) may be read by the CPU. It is recommended that the counter be stopped when reading to prevent potential problems that may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read. However, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in CTPU and CTPL. When the C/T clock divided by 16 is selected, the maximum divisor becomes 1,048,575. The CTS, RTS, CTS Enable Tx signals CTS (Clear To Send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. The CTS input is on pin I/O0 A for Tx A and on I/O1 A for Tx B. The CTS signal is active low; thus; it is called CTSN A for Tx A and CTSN B for Tx B. RTS is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. It is also active low and is, thus, called RTSN A for Rx A and RTSN B for Rx B. RTSN A is on pin I/O0 B and RTSN B is on I/O1 B. A receiver's RTSN output will usually be connected to the CTS input of the associated transmitter. Therefore, one could say that RTS and CTS are different ends of the same wire! MR2 (4) is the bit that allows the transmitter to be controlled by the CTS pin (I/O0 A or I/O1 A). When this bit is set to one AND the CTS input is driven high, the transmitter will stop sending data at the end of the present character being serialized. It is usually the RTS output of the receiver that will be connected to the transmitter's CTS input. The receiver will set RTS high when the receiver FIFO is full AND the start bit of the ninth character is sensed. Transmission then stops with nine valid characters in the receiver. When MR2 (4) is set to one, CTSN must be at zero for the transmitter to operate. If MR2 (4) is set to zero, the I/O pin will have no effect on the operation of the transmitter. MR1 (7) is the bit that allows the receiver to control I/O0 B. When the receiver controls I/O0 B (or I/O1 B), the meaning of that pin will be the RTSN function.
(2
Often this division will result in a non-integer number, 26.3 for example. One can only program integer numbers in a digital divider. Therefore, 26 would be chosen. This gives a baud rate error of 0.3/26.3, which is 1.14% and well within the ability asynchronous mode of operation. If the value in CTPU and CTPL is changed, the current half-period will not be affected, but subsequent half periods will be. The C/T will not be running until it receives an initial `Start Counter' command from the command register (or a read at address A6-A0 = 0001110 in the lower 16 position address space) . After this, while in timer mode, the C/T will run continuously. Receipt of a start counter command causes the counter to terminate the current timing cycle and to begin a new cycle using the values in CTPU and CTPL. The counter ready status bit (ISR [3]) is set once each cycle of the square wave. The bit is reset by a stop counter command from the command register (or a read with A6-A0 = 0x0F in the lower 16 position address space). The command however, does not stop the C/T. the generated square wave is output on I/O3 if it is programmed to be the C/T output. In the counter mode, the value C/T loaded into CTPU and CTPL by the CPU is counted down to 0. Counting begins upon receipt of a start counter command. Upon reaching terminal count H`0000', the counter ready interrupt bit (ISR [3]) is set. The counter continues counting past the terminal count until stopped by the CPU. If I/O3 is programmed to be the output of the C/T, the
2000 Feb 10
35
Philips Semiconductors
Objective specification
Dual UART
SC28L202
Registers of the Arbitrating Interrupt System and Bidding control
ICR - Interrupt Control Register Bits 7:0 Upper eight bits of the Arbitration Threshold This register provides a single 8-bit field called the interrupt threshold for use by the interrupt arbiter. The field is interpreted as a single unsigned integer. The interrupt arbiter will not generate an external interrupt request, by asserting IRQN, unless the value of the highest priority interrupt exceeds the value of the interrupt threshold. If the highest bidder in the interrupt arbitration is lower than the threshold level set by the ICR, the Current Interrupt Register, CIR, will contain 0x'00. Refer to the functional description of interrupt generation for details on how the various interrupt source bid values are calculated. NOTE: While a watch-dog Timer interrupt is pending, the ICR is not used and only receiver codes are presented for interrupt arbitration. This allows receivers with very low count values (perhaps below the CIR - Current Interrupt Register Bits 7:6 Type 00 = Type other than transmit or Receiver Bits 5:1 Current byte count/type 00000 = no interrupt 00001 = Change of State 00010 = Address Recognition 00011 = Xon/Xoff status 00100 = Receiver Watch dog 00101 = Break change 00110 = Counter Timer 00111 = Rx Loop Back Error Current count code 00000 => At least 1 character 00001 => At least 16 characters 00001 => At least 24 characters . . 11101 => At least 240 characters 11110 => At least 248 characters 11111 => 256 (See also GIBCR) Bits 0 Channel number or C/T number 0 = Channel A or C/T 0 1 = Channel B or C/T 1
threshold value) to win interrupt arbitration without requiring the user to explicitly lower the threshold level in the ICR. These bits are the upper seven (8) bits of the interrupt arbitration system. The lower three (3) bits represent the channel number. UCIR - Update CIR A command based upon a decode of address 0x8C. (UCIR is not a register!) A write (the write data is not important; a "don't care") to this 'register' causes the Current Interrupt Register to be updated with the value that is winning interrupt arbitration. The register would be used in systems that polls the interrupt status registers rather than wait for interrupts. Alternatively, the CIR is normally updated during an Interrupt Acknowledge Bus cycle in interrupt driven systems.
01 = Transmit 11 = Receive w errors 10 = Receive w/o errors
0=A 1=B
The Current Interrupt Register is provided to speed up the specification of the interrupting condition in the DUART. The CIR is updated at the beginning of an interrupt acknowledge bus cycle or in response to an Update CIR command. (see immediately above) Although interrupt arbitration continues in the background, the current interrupt information remains frozen in the CIR until another IACKN cycle or Update CIR command occurs. The LSBs of the CIR provide part of the addressing for various Global Interrupt registers including the GIBCR, GICR, GITR and the Global RxFIFO and TxFIFO FIFO. The host CPU need not generate individual addresses for this information since the interrupt context will remain stable at the fixed addresses of the Global Interrupt registers until IVR - Interrupt Vector Register Bits 7:0 8 data bits of the Interrupt Vector (IVR)
the CIR is updated. For most interrupting sources, the data available in the CIR alone will be sufficient to set up a service routine. The CIR may be processed as follows: If CIR[7] = 1, then a receiver interrupt is pending and the count is CIR[5:1], channel is CIR[0] Else If CIR[6] = 1 then a transmitter interrupt is pending and the count is CIR[5:1], channel is CIR[0] Else the interrupt is another type, specified in CIR[5:1] NOTE: The GIBCR, Global Interrupting Byte Count Register, may be read to determine an exact character count.
The IVR contains the byte that will be placed on the data bus during an IACKN cycle when the GCCR bits (2:1) are set to binary `01'. This is the unmodified form of the interrupt vector.
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36
Philips Semiconductors
Objective specification
Dual UART
SC28L202
Modification of the IVR Bits 7:3 Always contains bits (7:3) of the IVR Bits 2:1 Will be replaced with current interrupt type if IVC field of GCCR = 3 Bit 0 Replaced with interrupting channel number if IVC field of GCCR > 1
The table above indicates how the IVR may be modified by the interrupting source. The modification of the IVR as it is presented to the data bus during an IACK cycle is controlled by the setting of the bits (2:1) in the GCCR (Global Chip Configuration Register). GICR - Global Interrupting Channel Register Bits 7:1 Reserved Bit 0 Channel code 0=a 1=b
A register associated with the interrupting channel as defined in the CIR. It contains the channel number for the interrupting channel. GIBCR - Global Interrupting Byte Count Register Bits 7:0 Channel byte count code 00000001 = 1 00000010 = 2 . 11111111 = 255 00000000 = 256 A register associated with the interrupting channel as defined in the CIR. Its numerical value equals TxEL or RxFL at the time IACKN or "Update CIR" command was issued . The true number of bytes GITR - Global Interrupting Type Register Bit 7:6 Receiver Interrupt 0x = not receiver 10 = with receive errors 11 = w/o receive errors Bit 5 Transmitter Interrupt 0 = not transmitter 1 = transmitter interrupt Bit 4:3 Reserved read 0x00 Bit 2:0 Other types 000 = not "other" type 001 = Change of State 010 = Address Recognition Event 011 = Xon/Xoff status ready for transfer to the transmitter or transfer from the receiver. It is undefined for other types of interrupts
100 = Rx Watchdog 101 = Break Change 110 = Counter Timer 111 = Rx Loop Back Error
A register associated with the interrupting channel as defined in the CIR. It contains the type of interrupt code for all interrupts. GRxFIFO - Global RxFIFO Register Bits 7:0 8 data bits of RxFIFO. MSBs set to 0 for 7, 6, 5 bit data The RxFIFO of the channel indicated in the CIR channel field. Undefined when the CIR interrupt context is not a receiver interrupt. Global TxFIFO Register GTxFIFO - Global TxFIFO Register Bits 7:0 8 data bits of TxFIFO. MSBs not used for 7, 6, 5 bit data The TxFIFO of the channel indicated in the CIR channel field. Undefined when the CIR interrupt context is not a transmitter interrupt. Writing to the GTxFIFO when the current interrupt is not a transmitter event may result in the characters being transmitted on a different channel than intended. BCRBRK - Bidding Control Register - Break Change, A and B Bits 7:0 MSBs of break change interrupt bid This register provides the 8 MSBs of the Interrupt Arbitration number for a break change interrupt. BCRCOS - Bidding Control Register - Change of State, A and B Bits 7:0 MSBs of Change of state detectors (COS) interrupt bid This register provides the 8 MSBs of the Interrupt Arbitration number for a Change of State, COS, interrupt.
2000 Feb 10
37
Philips Semiconductors
Objective specification
Dual UART
SC28L202
BCRx - Bidding Control Register - Xon/Xoff, A and B Bits 7:0 MSBs of an Xon/Xoff interrupt bid This register provides the 8 MSBs of the Interrupt Arbitration number for a Xon/Xoff interrupt. BCRA - Bidding Control Register - Address, A and B Bits 7:0 MSBs of an address recognition event interrupt bid This register provides the 8 MSBs of the Interrupt Arbitration number for an address recognition event interrupt. BCR C/T - Bidding Control Register -C/T, 0 and 1 Bits 7:0 MSBs of a counter/timer event interrupt bid This register provides the 8 MSBs of the Interrupt Arbitration number for a counter/timer event interrupt. BCRLBE - Bidding Control Register - Received Loop Back Error Bits 7:0 MSBs of a received loop back error event interrupt bid This register provides the 8 MSBs of the Interrupt Arbitration number for the received loop back error interrupt.
Registers of the I/O ports
IPCRL - Input Port Change Register Lower Nibble, A and B (n = A for A, n = B for B) Bit 7 I/O3 n change 0 = no change 1 = change Bit 6 I/O2 n change 0 = no change 1 = change Bit 7 I/O1 n change 0 = no change 1 = change Bit 6 I/O0 n change 0 = no change 1 = change Bit 3 I/O3 n state Bit 2 I/O2 n state Bit 1 I/O1 n state Bit 0 I/O0 n state
Reads the actual logic level at the pin. 1 = high level; 0 = low level
This register may be read to determine the current logical level of the I/O pins and examine the output of the change detectors assigned to each pin. If the change detection is not enabled or if the pin is configured as an output, the associated change field will read b'0. IPCRU - Input Port Change Register Upper Nibble, A and B (n = A for A, n = B for B) Bit 7 I/O7 n change 0 = no change 1 = change Bit 6 I/O6 n change 0 = no change 1 = change Bit 7 I/O5 n change 0 = no change 1 = change Bit 6 I/O4 n change 0 = no change 1 = change Bit 3 Bit 2 Bit 1 I/O7 n state I/0n6 state I/O5 n state Reads the actual logic level at the pin. 1 = high level; 0 = low level Bit 0 I/O4 n state
This register may be read to determine the current logical level of the I/O pins and examine the output of the change detectors assigned to each pin. If the change detection is not enabled or if the pin is configured as an output, the associated change field will read b'0. IPR - Input Port Register, A and B (n = A for A, n = B for B) Bits 7:0 Logical levels of I/O(7:0)n IPCE - Input Change Detect Enable, A and B (n = A for A, n = B for B) Bit 7 I/O7 n enable 0 = disable 1 = enable Bit 6 I/O6 n enable 0 = disable 1 = enable Bit 5 I/O5 n enable 0 = disable 1 = enable Bit 4 I/O4 n enable 0 = disable 1 = enable Bit 3 I/O3 n enable 0 = disable 1 = enable Bit 2 I/O2 n enable 0 = disable 1 = enable Bit 1 I/O1 n enable 0 = disable 1 = enable Bit 0 I/O0 n enable 0 = disable 1 = enable
IPCE[7:0] bits activate the input change of state detectors. If a pin is configured as an output, the change of state detectors, if enabled, continue to be active and will show a change of state as the I/P port changes.
2000 Feb 10
38
Philips Semiconductors
Objective specification
Dual UART
SC28L202
I/OPCR 0 - I/O Port Configuration Register Bits 7:6 I/O3 A control 00 = GPI / TxC A 01 = OPR[3] A 10 = TxC A (16X) Output 11 = Reserved Bits 5:4 I/O2 A control 00 = GPI / CT 0 Clock Input 01 = OPR[2] A / DTRN A 10 = TxC A (1X) Output 11 = Reserved Bits 3:2 I/O1 A control 00 = GPI / CTSN B 01 = OPR[1] A 10 - 11 = Reserved Bits 1:0 I/O0 A control 00 = GPI / CTSN A 01 = OPR[0] A 10 - 11 = Reserved
I/OPCR 1 - I/O Port Configuration Register Bits 7:6 I/O7 A control 00 = GPI / CT 1 Clock Input 01 = OPR[7] A / DTRN B 10 = TxC B (1X) Output 11 = Reserved Bits 5:4 I/O6 A control 00 = GPI / RxC B / PBRG 1 Clk Input 01 = OPR[6] A 10 = RxC B (16X) Output 11 = Reserved Bits 3:2 I/O5 A control 00 = GPI / TxC B 01 = OPR[5] A 10 = TxC B (16X) Output 11 = Reserved Bits 1:0 I/O4 A control 00 = GPI / RxC A / PBRG 0 Clk Input 01 = OPR[4] A 10 = RxC A (16X) Output 11 = Reserved
I/OPCR 2 - I/O Port Configuration Register Bits 7:6 I/O3 B control 00 = GPI /DSRN B 01 = OPR[3] B 10 = RxC B (1X) Output 11 = C/T 0 Output (open drain) Bits 5:4 I/O2 B control 00 = GPI /DSRN A 01 = OPR[2] B 10 = RxC A (1X) Output 11 = C/T 1 Output (open drain) Bits 3:2 I/O1 B control 00 = GPI 01 = OPR[1] B / RTSN B 10 = Reserved 11 = Reserved Bits 1:0 I/O0 B control 00 = GPI 01 = OPR[0] B / RTSN B 10 = Reserved 11 = Reserved
I/OPCR 3 - I/O Port Configuration Register Bits 7:6 I/O7 B control 00 = GPI /RIN B 01 = OPR[7] B 10 =TxINTN B (open drain) 11 =reserved Bits 5:4 I/O6 B control 00 = GPI /RIN A 01 = OPR[6] B 10 =TxINTN A (open drain) 11 = reserved Bits 3:2 I/O5 B control 00 = GPI /DCDN B 01 = OPR[5] B 10 = RxINTN B (open drain) 11 = reserved Bits 1:0 I/O4 B control 00 = GPI /DCDN A 01 = OPR[4] B 10 = RxINTN A (open drain) 11 = reversed
NOTE: Both I/O Port A and B default to input upon a hardware reset to avoid hardware conflicts with I/O direction The four registers above contain 4, 2 bit fields that set the direction and source for each of the I/O pins associated with the channel. The I/O0 B or I/O1 B output may be RTSN if MR1[7] is set. It may also signal "end of transmission" if MR2[5] is set. (Please see the descriptions of these functions under the MR1 and MR2 register descriptions). The binary settings of the binary 00 combination always configures the I/O pins as "inputs". However the input circuit of the I/O pins are ALWAYS active. In actuality the binary 00 condition only disable the output driver of the pin. Since the input circuit and the associated change of state detector is always active the output signal may generate interrupts or drive counters. This register resets to 0x00 on reset, effectively configuring all I/O pins as inputs. Inputs may be used as RxC, TxC inputs or CTSN and General Purpose Inputs simultaneously. All inputs are equipped with change detectors that may be used to generate interrupts or can be polled, as required. SOPR A and SOPR B - Set the Output Port Bits (OPR A and OPR B) SOPR [7:0] - Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This allows software to set individual bits with our keeping a copy of the OPR bit configuration. One register for each channel. Set OPR Bits Bit 7 OPR 7 1=set bit 0=no change BIT 6 OPR 6 1=set bit 0=no change BIT 5 OPR 5 1=set bit 0=no change BIT 4 OPR 4 1=set bit 0=no change BIT 3 OPR 3 1=set bit 0=no change BIT 2 OPR 2 1=set bit 0=no change BIT 1 OPR 1 1=set bit 0=no change BIT 0 OPR 0 1=set bit 0=no change
2000 Feb 10
39
Philips Semiconductors
Objective specification
Dual UART
SC28L202
ROPR A and ROPR B - Reset ROPR Output Port Bits (OPR A and OPR B) ROPR [7:0] - Ones in the byte written to the ROPR will cause the effect. This allows software to reset individual bits with our keeping a corresponding bit positions in the OPR to set to 0. Zeros have no copy of the OPR bit configuration. One register for each channel Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Reset OPR OPR 7 OPR 6 OPR 5 OPR 4 OPR 3 OPR 2 OPR 1 OPR 0 Bits 1=reset bit 1=reset bit 1=reset bit 1=reset bit 1=reset bit 1=reset bit 1=reset bit 1=reset bit 0=no change 0=no 0=no 0=no 0=no 0=no 0=no 0=no change change change change change change change OPR - Output Port Register, A and B (n = A for A, n = B for B) The output pins (I/O pins) drive the data written to this register. Bit 7 BIT 6 BIT 5 BIT 4 OPR I/O7 n I/O6 n I/O5 n I/O4 n 0=Pin High 0=Pin High 0=Pin High 0=Pin High 1=Pin Low 1=Pin Low 1=Pin Low 1=Pin Low This register is set by the SOPR and ROPR above.
BIT 3 I/O3 n 0=Pin High 1=Pin Low
BIT 2 I/O2 n 0=Pin High 1=Pin Low
BIT 1 I/O1 n 0=Pin High 1=Pin Low
BIT 0 I/O0 n 0=Pin High 1=Pin Low
THE REGISTERS FOR COMPATIBILITY WITH PREVIOUS DUARTS
The purpose of including previous functionality is to allow users to call communications code that may be used in former systems. When the registers in this lower 16-position address space is used it will revoke programming done in the upper address space where the addresses are duplicated. If functions have been called from upper address space that DO NOT exist in the lower address space they will remain active. It is therefore recommended that the "Reset to C92 " command be issued before calling code written for older devices. This is just recommended. If one wishes to enhance previous code by using Xon/Xoff, for example, there is no restriction against it. These registers provide the original functionality of previous Philips DUARTs: SCN2681, SCN68681, SCC2691, SCC68692, SC26C92 and SC28L92.
Table 7. SC28L92 Register Addressing READ (RDN = 0) WRITE (WRN = 0)
Address 0 00 0 00 0 01 0 01 0 10 0 10 0 11 0 11 1 00 1 00 1 01 1 01 1 10 1 10 1 11 1 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 READ (RDN = 0) Mode Register A (MR0 A, MR1 A, MR2 A) Status Register A (SR A) Reserved Rx Holding Register A (RxFIFO A) Input Port Change Register (IPCR) Interrupt Status Register (ISR) Counter/Timer Upper (CTPU) Counter/Timer Lower (CTPL) Mode Register B (MR0 B, MR1 B, MR2 B) Status Register B (SR B) Reserved Rx Holding Register B (RxFIFO B) IVR or general purpose register Input Port (IPR) I/O(6:0) A Start Counter Command (C/T 0) Stop Counter Command (C/T 0) WRITE (WRN = 0) Mode Register A (MR0 A, MR1 A, MR2 A) Clock Select Register A (CSR A ) Command Register A (CR A) Tx Holding Register A (TxFIFO A) Aux. Control Register (ACR) Interrupt Mask Register (IMR) C/T Upper Preset Register (CTPU) C/T Lower Preset Register (CTPL) Mode Register B (MR0 B, MR1 B, MR2 B) Clock Select Register B (CSR B ) Command Register B (CR B) Tx Holding Register B (TxFIFO B) IVR or general purpose register Output Port Confide. Register (OPCR) I/O(7:2) B Set Output Port Bits Command (SOPR) I/O(7:0) B Reset output Port Bits Command (ROPR) I/O(7:0) B
NOTE: The three MR Registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits)
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40
Philips Semiconductors
Objective specification
Dual UART
SC28L202
The following registers are unique for each Channel Mode Register MRn A MRn B R/W Status Register SR A SR B R only Clock CSR A CSR B W only Select Command Register Receiver FIFO Transmitter FIFO CR A RxFIFO A TxFIFO A CR B RxFIFO B TxFIFO B W only R only W only
These registers support functions for both Channels Input Port Change Register IPCR R Auxiliary Control Register ACR W Interrupt Status Register ISR R Interrupt Mask Register IMR W Counter Timer Upper Value CTPU R Counter Timer Lower Value CTPL R Counter Timer Preset Upper CTPU W Counter Timer Preset Lower CTPL W Input Port Register IPR R Output Configuration Register OPCR W Set Output Port Bits W Reset Output Port Bits W
Table 8. Baud Rate Generator Characteristics
Crystal or Clock = 14.7456 MHz NORMAL RATE (BAUD) ACTUAL 16X CLOCK (KHz) ERROR (%) 0 0 -0.069 0.059 0 0 0 0 -0.260 0 0 0.175 NORMAL RATE (BAUD) 2400 4800 7200 9600 19.2K 38.4K 14.4K 28.8K 31.25 57.6k 115.2K 230.4K ACTUAL 16X CLOCK (KHz) 38.4 76.8 115.2 153.6 307.2 614.4 230.4 460.8 500.0 921.6 1843.2 3686.4 ERROR (%) 0 0 0 0 0 0 0 0 1.6 0 0 0
50 0.8 75 1.2 110 1.759 134.5 2.153 150 2.4 200 3.2 300 4.8 600 9.6 1050 16.756 1200 19.2 1800 28.8 2000 32.056 NOTE: Duty cycle of 16X clock is 50% 1%
2000 Feb 10
41
Philips Semiconductors
Objective specification
Dual UART
SC28L202
REGISTER DESCRIPTIONS Mode Registers MR0 Mode Register 0 MR0 is accessed by setting the MR pointer to 0 via the command register command B. MR0 A MR0 B MR0 B[3:0] are reserved Bit 7 Rx WATCH DOG 0 = Disable 1 = Enable BIT 6 RxINT BIT 2 See Tables in MR0 description BIT (5:4) TxINT (1:0) See table #4 BIT 3 FIFO Size 0=8 1 = 256 BIT 2 BAUD RATE EXTENDED II 0 = Norma 1 = Extend II BIT 1 TEST 2 Set to 0 BIT 0 BAUD RATE EXTENDED 1 0 = Normal 1 = Extend
MR0[7] This bit controls the receiver watchdog timer. 0 = disable, 1 = enable. When enabled, the watch dog timer will generate a receiver interrupt if the receiver FIFO has not been accessed within 64 bit times of the receiver 1X clock. This is used to alert the control processor that data is in the RxFIFO that has not been read. This situation may occur when the byte count of the last part of a message is not large enough to generate an interrupt. This control bit is duplicated WCXER(7:6) MR0[6] - Bit 2 of receiver FIFO interrupt level. This bit along with Bit 6 of MR1 sets the fill level of the 8 byte FIFO that generates the receiver interrupt. MR0[6] MR1[6] Note that this control is split between MR0 and MR1. This is for backward compatibility to the SC2692 and SCN2681.
Table 11. Transmitter FIFO Interrupt Fill Level MR0(3)=0
MR0[5:4] 00 01 10 11 Interrupt Condition 8 bytes empty (Tx EMPTY) 4 or more bytes empty 6 or more bytes empty 1 or more bytes empty (Tx RDY)
Table 12. Transmitter FIFO Interrupt Fill Level MR0(3)=1
MR0[5:4] 00 01 10 11 Interrupt Condition 256 bytes empty (Tx EMPTY) 128 or more bytes empty 192 or more bytes empty 1 or more bytes empty (Tx RDY)
Table 9. Receiver FIFO Interrupt Fill Level MR0(3)=0
MR0[6] MR1[6] 00 01 10 11 Interrupt Condition 1 or more bytes in FIFO (Rx RDY) 3 or more bytes in FIFO 6 or more bytes in FIFO 8 bytes in FIFO (Rx FULL)
Table 10. Receiver FIFO Interrupt Fill Level MR0(3)=1
MR0[6] MR1[6] 00 01 10 11 Interrupt Condition 1 or more bytes in FIFO (Rx RDY) 128 or more bytes in FIFO 192 or more bytes in FIFO 256 bytes in FIFO (Rx FULL)
For the transmitter these bits control the number of FIFO positions empty when the receiver will attempt to interrupt. After the reset the transmit FIFO has 8 bytes empty. It will then attempt to interrupt as soon as the transmitter is enabled. The default setting of the MR0 bits (00) condition the transmitter to attempt to interrupt only when it is completely empty. As soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request. MR0[3] - FIFO Size MR0[2:0] - These bits are used to select one of the six-baud rate groups. See Table 13 for the group organization.
For the receiver these bits control the number of FIFO positions empty when the receiver will attempt to interrupt. After the reset the receiver FIFO is empty. The default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it. MR0[5:4] - Tx interrupt fill level.
* 000 Normal mode * 001 Extended mode I * 100 Extended mode II
Other combinations of MR2[2:0] should not be used NOTE: MR0[3:0] are not used in channel B and should be set to 0.
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
MR1 Mode Register 1 MR1 A MR1 B Bit 7 Rx CONTROLS RTS 0 = No 1 = Yes BIT 6 RxINT BIT 1 BIT 5 ERROR MODE Bit (4:3) PARITY MODE BIT 2 PARITY TYPE Bits (1:0) BITS PER CHARACTER 00 = 5 01 = 6 10 = 7 11 = 8
0 = RxRDY 1 = FFULL
0 = Char 1 = Block
00 = With Parity 01 = Force Parity 10 = No Parity 11 = Multi-drop Mode
0 = Even 1 = Odd
NOTE: * In block error mode the block error conditions must be cleared by using the error reset command (command 0x40) or a receiver reset. MR1 A is accessed when the Channel A MR pointer points to MR1. The pointer is set to MR1 by RESET or by a `set pointer' command applied via CR command 1. After reading or writing MR1 A, the pointer will point to MR2 A. MR1 A[7] - Channel A Receiver Request-to-Send Control (Flow Control) This bit controls the deactivation of the RTSN A output (I/O0 B) by the receiver. This output is normally asserted by setting OPR[0]B and negated by resetting OPR[0]B. MR1 A[7] = 1 causes RTSN A to be negated (I/O0 B is driven to a `1' [VCC]) upon receipt of a valid start bit if the Channel A FIFO is full. This is the beginning of the reception of the ninth byte. If the FIFO is not read before the start of the tenth byte, an overrun condition will occur and the tenth byte will be lost. However, the bit in OPR[0] is not reset and RTSN A will be asserted again when an empty FIFO position is available. This feature can be used for flow control to prevent overrun in the receiver by using the RTSN A output signal to control the CTSN input of the transmitting device. MR1[6] - Receiver interrupt control bit 1. See description under MR0[6]. MR1 A[5] - Channel A Error Mode Select This bit select the operating mode of the three FIFOed status bits (FE, PE, received break) for Channel A. In the `character' mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the `block' MR2 Mode Register 2 MR2 A MR2 B Bit 7 BIT 6 CHANNEL MODE BIT 5 Tx CONTROLS RTS BIT 4 CTS ENABLE Tx BIT 3 BIT 2 BIT 1 BIT 0 STOP BIT LENGTH NOTE: Add 0.5 to binary codes 0 - 7 for 5 bit character lengths. 0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813 1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875 2 = 0.688 6 = 0.938 A = 1.688 E = 1.938 3 = 0.750 7 = 1.000 B = 1.750 F = 2.000 See description in the previous MR2 description mode, the status provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last `reset error' command for Channel A was issued. MR1 A[4:3| - Channel A Parity Mode Select If `with parity' or `force parity' is selected a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data MR1 A[4:3] = 11 selects Channel A to operate in the special multi-drop mode described in the Operation section. MR1 A[2] - Channel A Parity Type Select Selects the parity type (odd or even) if the "`with parity" mode is programmed by MR1 A[4:3], and the polarity of the forced parity bit if the `force parity' mode is programmed; no effect if `no parity' is programmed. In the special multi-drop mode it selects the polarity of the A/D bit. MR1 A[1:0] - Channel A Bits Per Character Select This field selects the number of data bits per character to be transmitted and received. The character length does not include the start, parity, and stop bits. MR2 A is accessed when the Channel A MR pointer points to MR2, which occurs after any access to MR1 A. Accesses to MR2 A do not change the pointer.
00 = Normal 0 = No 0 = No 01 = Auto-Echo 1 = Yes 1 = Yes 10 = Local loop 11 = Remote loop NOTE: *Add 0.5 to values shown for 0 - 7 if channel is programmed for 5 bits/char.
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Philips Semiconductors
Objective specification
Dual UART
SC28L202
SR Status Register SR A SR B Bit 7 RECEIVED BREAK* 0 = No 1 = Yes BIT 6 FRAMING ERROR* 0 = No 1 = Yes BIT 5 PARITY ERROR* 0 = No 1 = Yes BIT 4 OVERRUN ERROR 0 = No 1 = Yes BIT 3 TxEMT 0 = No 1 = Yes BIT 2 TxRDY 0 = No 1 = Yes BIT 1 FFULL 0 = No 1 = Yes BIT 0 RxRDY 0 = No 1 = Yes
NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a "reset error status" command. In character mode they are discarded when the corresponding data character is read from the FIFO. In block error mode, the error-reset command (command 4x or receiver reset) must used to clear block error conditions SR A[7] - Received Break Channel A Received Break. This bit indicates that an all zero character of the programmed length has been received without a stop bit. Only a single FIFO position is occupied when a break is received: further entries to the FIFO are inhibited until the RxD A line returns to the marking state for at least one-half a bit time two successive edges of the internal or external 1X clock. This will usually require a high time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock. When this bit is set, the Channel A `change in break' bit in the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break condition, as defined above, is detected. The break detect circuitry can detect breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until at least the end of the next character time in order for it to be detected. This bit is reset by command 4 (0100) written to the command register or by receiver reset. SR A[6] - Channel A Framing Error This bit, when set, indicates that a stop bit was not detected when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position. SR A[5] - Channel A Parity Error This bit is set when the `with parity' or `force parity' mode is programmed and the corresponding character in the FIFO was received with incorrect parity. In the special multi-drop mode the parity error bit stores the receive A/D (Address/Data) bit. SR A[4] - Channel A Overrun Error This bit, when set, indicates that one or more characters in the received data stream have been lost. It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. This bit is cleared by a `reset error status' command.
SR A[3] - Channel A Transmitter Empty (TxEMT A) This bit will be set when the transmitter under runs, i.e., both the TxEMT and TxRDY bits are set. This bit and TxRDY are set when the transmitter is first enabled and at any time it is re-enabled after either (a) reset, or (b) the transmitter has assumed the disabled state. It is always set after transmission of the last stop bit of a character if no character is in the THR awaiting transmission. It is reset when the THR is loaded by the CPU, a pending transmitter disable is executed, the transmitter is reset, or the transmitter is disabled while in the under run condition. SR A[2] - Channel A Transmitter Ready (TxRDY A) This bit, when set, indicates that the transmit FIFO is not full and ready to be loaded with another character. This bit is cleared when the transmit FIFO is loaded by the CPU and there are (after this load) no more empty locations in the FIFO. It is set when a character is transferred to the transmit shift register. TxRDY A is reset when the transmitter is disabled and is set when the transmitter is first enabled. Characters loaded to the TxFIFO while this bit is 0 will be lost. This bit has different meaning from ISR[0]. SR A[1] - Channel A FIFO Full (FFULL A) This bit is set when a character is transferred from the receive shift register to the receive FIFO and the transfer causes the FIFO to become full, i.e., all eight FIFO positions are occupied. It is reset when the CPU reads the receive FIFO. If a character is waiting in the receive shift register because the FIFO is full, FFULL A will not be reset when the CPU reads the receive FIFO. This bit has different meaning from ISR1 when MR1 6 is programmed to a `1'. SR A[0] - Channel A Receiver Ready (RxRDY A) This bit indicates that a character has been received and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and reset when the CPU reads the receive FIFO, only if (after this read) there are no more characters in the FIFO. SR B - Channel B Status Register The bit definitions for this register are identical to the bit definitions for SR A, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and outputs.
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44
Philips Semiconductors
Objective specification
Dual UART
SC28L202
CSR A - Channel A Clock Select Register CSR A [7:4] - Channel A Receiver Clock Select This field selects the baud rate clock for the Channel A receiver. The field definition is shown in Table 13. CSR Clock Select Register CSR A & CSR B Bit 7 BIT 6 BIT 5 RECEIVER CLOCK SELECT See Text and Table 13 BIT 4 BIT 3 BIT 2 BIT 1 TRANSMITTER CLOCK SELECT See Text and Table 13 BIT 0
Table 13. Baud Rate (Base on a 14.7456 MHz crystal clock)
CSR A [7:4] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MR0[0] = 0 (Normal Mode) ACR[7] = 0 ACR[7] = 1 50 75 110 110 134.5 134.5 200 150 300 300 600 600 1,200 1,200 1,050 2,000 2,400 2,400 4,800 4,800 7,200 1,800 9,600 9,600 38.4K 19.2K Timer Timer I/O4 A-16X I/O4 A-16X I/O4 A-1X I/O4 A-1X MR0[0] = 1 (Extended Mode I) ACR[7] = 0 ACR[7] = 1 300 450 110 110 134.5 134.5 1200 900 1800 1800 3600 3600 7200 7,200 1,050 2,000 14.4K 14.4K 28.8K 28.8K 7,200 1,800 57.6K 57.6K 230.4K 115.2K Timer Timer I/O4 A-16X I/O4 A-16X I/O4 A-1X I/O4 A-1X MR0[2] = 1 (Extended Mode II) ACR[7] = 0 ACR[7] = 1 4,800 7,200 880 880 1,076 1,076 19.2K 14.4K 28.8K 28.8K 57.6K 57.6K 115.2K 115.2K 1,050 2,000 57.6K 57.6K 4,800 4,800 57.6K 14.4K 9,600 9,600 38.4K 19.2K Timer Timer I/O4 A-16X I/O4 A-16X I/O4 A-1X I/O4 A-1X
NOTE: The receiver clock is always a 16X clock except for CSR A [7:4] = 1111. CSR A [3:0] - Channel A EXTERNAL Transmitter Clock Select The receiver clock is always a 16X clock except for CSR B [7:4] = This field selects the baud rate clock for the Channel A transmitter. 1111. The field definition is as shown in Table 13, except as follows: CSR B [3:0] - Channel B Transmitter Clock Select CSR A [3:0] ACR[7] = 0 ACR[7] = 1 This field selects the baud rate clock for the Channel B transmitter. 1110 I/O3 A-16X I/O3 A-16X The field definition is as shown in Table 13, except as follows: 1111 I/O3 A-1X I/O3 A-1X CSR B [3:0] ACR[7] = 0 ACR[7] = 1 The transmitter clock is always a 16X clock except for CSR[3:0] = 1111. CSR B [7:4] - Channel B Receiver Clock Select This field selects the baud rate clock for the Channel B receiver. The field definition is as shown in Table 13, except as follows: CSR B [7:4] 1110 111 ACR[7] = 0 I/O6 A-16X I/O6 A-1X ACR[7] = 1 I/O6 A-16X I/O6 A-1X 1110 1111 I/O5 A-16X I/O5 A-1X I/O5 A-16X I/O5 A-1X
The transmitter clock is always a 16X clock except for CSR B [3:0] = 1111.
Rx FIFO Register. For characters shorter than 8 bits the unused bits are set to zero Bit 7 BIT 6 BIT 5 Bits of the received data characters. BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Tx FIFO register. For characters shorter than 8 bits the unused bits are set to zero Bit 7 BIT 6 BIT 5 Bits of the data characters to be transmitted BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CR A and B Command Register CR, one for each channel, controls the channel commands and enables/disables the receiver and transmitter. Commands may be to
the upper and lower four bits in the same bus cycle. If both enable and disable bits are set to 1 in the lower four bits a disable will result.
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45
Philips Semiconductors
Objective specification
Dual UART
SC28L202
CR Command Register CR A &CR B Bit 7 BIT 6 BIT 5 MISCELLANEOUS COMMANDS See Text of Channel Command Register BIT 4 BIT 3 Disable Tx 1 = Yes 0 = No BIT 2 Enable Tx 1 = Yes 0 = No BIT 1 Disable Rx 1 = Yes 0 = No BIT 0 Enable Rx 1 = Yes 0 = No
NOTE: Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded. COMMAND REGISTER TABLE A and B Commands 0xE, 0xF (marked with *) are global and exist only in channel A's register space. Channel Command Code CR[7:4] 0000 0001 0010 0011 0100 0101 0110 0111 Channel Command Description NOP Set MR pointer to 1 Reset Receiver Reset Transmitter Reset Error Status Reset Break Change Interrupt Begin Transmit Break End Transmit Break Channel Command Code CR[7:4] 1000 1001 1010 1011 1100 1101 1110 1111 Channel Command Description Assert RTSN (I/O0 B or I/O1 B) Negate RTSN (I/O0 B or I/O1 B) Set C/T Receiver time-out mode on Set MR pointer to 0 Set C/T Receiver time-out mode off Block Error Status on RxFIFO load * Power Down Mode On * Disable Power Down Mode
* 0000 No command. * 0001 set MR pointer to 1 * 0010 Reset receiver. Immediately resets the receiver as if
hardware reset had been applied. The receiver is reset and the FIFO pointer is reset to the first location effectively discarding all unread characters in the FIFO.
* 0111 Stop break. The TxD line will go high (marking) within two bit
times. TxD will remain high for one bit time before the next character is transmitted.
* 1000 Assert RTSN. Causes the RTSN output to be asserted (low). * 1001 Negate RTSN. Causes the RTSN output to be negated
(high). NOTE: The two commands above actually reset and set, respectively, the I/O0 B or I/O1 B pin associated WITH the OPR register.
* 0011 Reset transmitter. Immediately resets the transmitter as if a
hardware reset had been applied. The transmitter is reset and the FIFO pointer is reset to the first location effectively discarding all untransmitted characters in the FIFO.
* 0100 Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register (SR[7:4]). I It is used in either character or block mode. In block mode it would normally be used after the block is read. change bit in the interrupt status register (ISR[2]) to be cleared to zero.
* 1010 Set C/T Receiver time out mode on. The receiver in this
channel will restart the C/T as reach receive character is transferred from the shift register to the RxFIFO. The C/T is placed in the Counter Mode, the Start/Stop Counter commands are disabled, the counter is stopped and the Counter Ready bit, ISR(3), is reset.
* 0101 Reset break change interrupt. Causes the break detect * 0110 Start break. Forces the TxD output low (spacing). If the
* 1011 Set MR Pointer to 0 * 1100 Set C/T Receiver time out mode off * 1101 Block error status accumulation on FIFO entry. Allows the
"received break", "framing error" and "parity error" bits to be set as the received character is loaded to the RxFIFO. (normally these bits are set on reading of the data from the RxFIFO) Setting this mode can give information about error data up to 256 bytes earlier than the normal mode. However it clouds the ability to know precisely which byte(s) are in error.
transmitter is empty, the start of the break condition will be delayed up to two bit times. If the transmitter is active and the TxFIFO is empty then the break begins when transmission of the current character is completed. If there are characters in the TxFIFO, the start of break is delayed until all characters presently in the TxFIFO and any subsequent characters loaded have been transmitted. (Tx Idle must be true before break begins). The transmitter must be enabled to start a break.
* 1110 Power Down Mode On * 1111 Disable Power Down Mode
2000 Feb 10
46
Philips Semiconductors
Objective specification
Dual UART
SC28L202
IPCR Input Port Configuration Register IPCR Bit 7 Delta I/O 3A 0 = no change 1 = change BIT 6 Delta I/O 2A 0 = no change 1 = change BIT 5 Delta I/O 1A 0 = no change 1 = change BIT 4 Delta I/O 0A 0 = no change 1 = change BIT 3 I/O 3A 0 = low 1 = High BIT 2 I/O 2A 0 = low 1 = High BIT 1 I/O 1A 0 = low 1 = High BIT 0 I/O 0A 0 = low 1 = High
IPCR [7:4] I/03A, I/O2 A, I/O1 A, I/O0 A Change-of-State These bits are set when a change-of-state, as defined in the input port section of this data sheet, occurs at the respective input pins. They are cleared when the IPCR is read by the CPU. A read of the IPCR also clears ISR [7], the input change bit in the interrupt status register. The setting of these bits can be programmed to generate an interrupt to the CPU. ACR Auxiliary Control Register Bit 7 BRG SET Select 0 = set 1 1 = set 2 BIT 6 BIT 5 BIT 4 Counter Timer Mode and clock source select See Table 14
IPCR [3:0] I/O3 A, I/O2 A, I/O1 A, I/O0 A logical level of I/O pin. These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read.
ACR
BIT 3 Delta I/O3 A interrupt enable 0 = off 1 = enabled
BIT 2 Delta I/O2 A interrupt enable 0 = off 1 = enabled
BIT 1 Delta I/O1 A interrupt enable 0 = off 1 = enabled
BIT 0 Delta I/O0 A interrupt enable 0 = off 1 = enabled
ACR[7] - Baud Rate Generator Set Select This bit selects one of two sets of baud rates to be generated by the BRG and it effects both channels. (see Table 13). ACR[6:4] - Counter/Timer Mode And Clock Source Select This field selects the operating mode of the counter/timer and its clock source as shown in Table 14. ACR [3:0] - I/O3 A, I/O2 A, I/O1 A, I/O0 A Change-of-State Interrupt Enable This field selects which bits of the input port change register (IPCR) cause the input change bit in the interrupt status register (ISR [7]) to be set. If a bit is in the `on' state the setting of the corresponding bit in the IPCR will also result in the setting of ISR [7], which results in the generation of an interrupt output if IMR [7] = 1. If a bit is in the `off' state, the setting of that bit in the IPCR has no effect on ISR [7].
Table 14. ACR 6:4 Field Definition
ACR(6:4) 000 001 010 MODE Counter Counter Counter CLOCK SOURCE External (I/02A) TxC A - 1X clock of Channel A transmitter TxC B - 1X clock of Channel B transmitter
011 Counter (X1/Sclk) clock divided by 16 100 Timer External (I/O 2A) 101 Timer External (I/O2 A) divided by 16 110 Timer Crystal or external clock (X1/Sclk) 111 Timer (X1/Sclk) clock divided by 16 NOTE: The timer mode generates a square wave.
2000 Feb 10
47
Philips Semiconductors
Objective specification
Dual UART
SC28L202
ISR - Interrupt Status Register This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR). If a bit in the ISR is a `1' and the corresponding bit in the IMR is also a `1' then INTRN output will be asserted (Low). If the ISR Bit 7 INPUT PORT CHANGE 0=not enabled 1=enabled BIT 6 DELTA Break B 0=not enabled 1=enabled BIT 5 RxRDY/ FFULL B 0=not enabled 1=enabled BIT 4 TxRDY B
corresponding bit in the IMR is a zero the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR - the true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to H`00' when the DUART is reset. BIT 3 Counter Ready 0=not enabled 1=enabled BIT 2 Delta Break A 0=not enabled 1=enabled BIT 1 RxRDY/ FFULL A 0=not enabled 1=enabled BIT 0 TxRDY A
0=not enabled 1=enabled
0=not enabled 1=enabled
ISR[7] - Input Port Change Status This bit is a `1' when a change-of-state has occurred at the I/O(3:0)A or B inputs and that event has been selected to cause an interrupt by the programming of ACR[3:0]. The bit is cleared when the CPU reads the IPCR. ISR[6] - Channel B Change In Break This bit, when set, indicates that the Channel B receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a Channel B `reset break change interrupt' command. ISR[5] - Rx B Interrupt This bit indicates that the channel B receiver is interrupting according to the fill level programmed by the MR0 and MR1 registers. This bit has a different meaning than the receiver ready/full bit in the status register. ISR[4] - Tx B Interrupt This bit indicates that the channel B transmitter is interrupting according to the interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning than the Tx RDY bit in the status register. ISR[3] - Counter Ready. In the counter mode, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command. In the timer mode, this bit is set once each cycle of the generated square wave (every other time that the counter/timer reaches zero IMR Bit 7 INPUT PORT CHANGE 0=not enabled 1=enabled BIT 6 Delta Break B 0=not enabled 1=enabled BIT 5 RxRDY/ FFULL B 0=not enabled 1=enabled BIT 4 TxRDY B 0=not enabled 1=enabled
count). The bit is reset by a stop counter command. The command, however, does not stop the counter/timer. ISR[2] - Channel A Change in Break This bit, when set, indicates that the Channel A receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a Channel A `reset break change interrupt' command. ISR[1] - Rx A Interrupt This bit indicates that the channel A receiver is interrupting according to the fill level programmed by the MR0 and MR1 registers. This bit has a different meaning than the receiver ready/full bit in the status register. ISR[0] - Tx A Interrupt This bit indicates that the channel A transmitter is interrupting according to the interrupt level programmed in the MR0[5:4] bits. This bit has a different meaning than the Tx RDY bit in the status register. IMR - Interrupt Mask Register The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a `1' and the corresponding bit in the IMR is also a `1' the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the programmable interrupt outputs I/O3 B-I/O7 B or the reading of the ISR.
BIT 3 Counter Ready 0=not enabled 1=enabled
BIT 2 Delta Break A 0=not enabled 1=enabled
BIT 1 RxRDY/ FFULL A 0=not enabled 1=enabled
BIT 0 TxRDY A 0=not enabled 1=enabled
CTPU Counter Timer Preset Upper (Counter/Timer 0) CPTU Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 The upper eight (8) bits for the 16 bit counter timer preset register BIT 2 BIT 1 BIT 0
CTPL Counter -Timer Preset Lower (Counter/Timer 0) CTPL Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 The lower eight (8) bits for the 16 bit counter timer preset register BIT 2 BIT 1 BIT 0
CTVU Counter Timer Value Upper (Counter/Timer 0) CPVL Bit 7 BIT 6 BIT 5 BIT 4 The lower eight (8) bits for the 16 bit counter timer value BIT 3 BIT 2 BIT 1 BIT 0
2000 Feb 10
48
Philips Semiconductors
Objective specification
Dual UART
SC28L202
CTVL Counter -Timer Value Lower (Counter/Timer 0) CTVL Bit 7 BIT 6 BIT 5 BIT 4 BIT 3 The lower eight (8) bits for the 16 bit counter timer value register BIT 2 BIT 1 BIT 0
Only the counter/timer 0 is available in the low order 16-position address map. Issuing the start command loads the C/T with the preset value. The Stop command resets the C/T ready bit in the ISR (Interrupt status Register) and captures the C/T value in the output
latches of the C/T. In the special time out mode the start and stop commands are ignored. The "start command is executed by a read at address 0xE; the stop at 0xF.
IVR Interrupt Vector register in 68K mode and General purpose read write register in the x86 mode IVR Bit 7 BIT 6 BIT 5 BIT 4 The eight (8) bits of the interrupt vector in the 68K mode. BIT 3 BIT 2 BIT 1 BIT 0
IPR Input Port Register I/O(6:0) A IPR Bit 7 BIT 6 BIT 5 Logical levels or the I/O[6:0] A, Bit 7 read as "1" BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OPCR Output Port Configuration Register. Controls [7:2] B Bit 7 I/O7 B 0 = OPR[7] 1 = Tx RDY B BIT 6 I/O6 B 0 = OPR[6] 1 = Tx RDY A BIT 5 I/O5 B 0 = OPR[5] 1 = Rx RDY / FFULL B BIT 4 I/O4 B 0 = OPR[4] 1 = Rx RDY / FFULL A BIT (3:2) I/O3 B 00 = OPR[3] 01 = C/T OUTPUT 10 = TxC B(1X) 11 = RxC B(1X) BIT (1:0) I/O2 B 00 = OPR[2] 01 = TxC A(16X) 10 = TxC A(1X) 11 = RxC A(1X)
NOTE: I/O0 B and I/O1 B output OPR(0) and OPR(1) respectively. Under program control of MR1 and MR2 the signals RTSN A for I/O0 B and RTSN B for I/O1 B may be assigned. OPCR[7] -This bit programs the I/O7 B output to provide one of the following:
open-drain output. Note that this output is not masked by the contents of the IMR. OPCR[3:2] -This bit programs the I/O3 B output to provide one of the following:
* 0 The complement of OPR[7]. * 1 The Channel B transmitter interrupt output which is the
* 00 The complement of OPR[3]. * 01 The counter/timer output, in which case I/O3 acts as an
complement of ISR[4]. When in this mode I/O7 acts as an open- drain output. Note that this output is not masked by the contents of the IMR. OPCR[6] -This bit programs the I/O6 B output to provide one of the following:
open-drain output. In the timer mode, this output is a square wave at the programmed frequency. In the counter mode, the output remains high until terminal count is reached, at which time it goes low. The output returns to the high state when the counter is stopped by a stop counter command. Note that this output is not masked by the contents of the IMR.
* 0 The complement of OPR[6]. * 1 The Channel A transmitter interrupt output which is the
* 10 The 1X clock for the Channel B transmitter that shifts the
transmitted data. If data is not being transmitted, a free running 1X clock is output.
complement of ISR[0]. When in this mode I/O6 acts as an open- drain output. Note that this output is not masked by the contents of the IMR. OPCR[5] -This bit programs the I/O5 B output to provide one of the following:
* 11 The 1X clock for the Channel B receiver that samples the
received data. If data is not being received, a free running 1X clock is output. OPCR[1:0] -This field programs the I/O2 B output to provide one of the following:
* 0 The complement of OPR[5]. * 1 The Channel B receiver interrupt output which is the
complement of ISR[5]. When in this mode I/O5 acts as an open-drain output. Note that this output is not masked by the contents of the IMR. OPCR[4] -This field programs the I/O4 B output to provide one of the following:
* 00 The complement of OPR[2]. * 01 The 16X clock for the Channel A transmitter. This is the clock
selected by CSR A [3:0], and will be a 1X clock if CSR A [3:0] = 1111.
* 10 The 1X clock for the Channel A transmitter that shifts the
transmitted data. If data is not being transmitted, a free running 1X clock is output.
* 0 The complement of OPR[4]. * 1 The Channel A receiver interrupt output which is the
* 11 The 1X clock for the Channel A receiver that samples the
received data. If data is not being received, a free running 1X clock is output.
complement of ISR[1]. When in this mode I/O4 acts as an
2000 Feb 10
49
Philips Semiconductors
Objective specification
Dual UART
SC28L202
SOPR - Set Bits in the OPR Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This allows software to set individual bits without keeping a copy of the OPR bit configuration. Set OPR Bits Bit 7 I/O7 B 1=set bit 0=no change BIT 6 I/O6 B 1=set bit 0=no change BIT 5 I/O5 B 1=set bit 0=no change BIT 4 I/O4 B 1=set bit 0=no change BIT 3 I/O3 B 1=set bit 0=no change BIT 2 I/O2 B 1=set bit 0=no change BIT 1 I/O1 B 1=set bit 0=no change BIT 0 I/O0 B 1=set bit 0=no change
ROPR - Reset Bits in the OPR Ones in the byte written to the ROPR will cause the corresponding bit positions in the OPR to set to 0. Zeros have no effect. This allows software to reset individual bits with our keeping a copy of the OPR bit configuration. Reset OPR Bits Bit 7 I/O7 B 1=reset bit 0=no change BIT 6 I/O6 B 1=reset bit 0=no change BIT 5 I/O5 B 1=reset bit 0=no change BIT 4 I/O4 B 1=reset bit 0=no change BIT 3 I/O3 B 1=reset bit 0=no change BIT 2 I/O2 B 1=reset bit 0=no change BIT 1 I/O1 B 1=reset bit 0=no change BIT 0 I/O0 B 1=reset bit 0=no change
OPR Output Port Register The bits in the OPR register are controlled by the use of the SOPR and ROPR commands. The output pins (OP pins) drive the compliment of the data stored in this register. OPR Bit 7 I/O7 B 0=Pin High 1=Pin Low BIT 6 I/O6 B 0=Pin High 1=Pin Low BIT 5 I/O5 B 0=Pin High 1=Pin Low BIT 4 I/O4 B 0=Pin High 1=Pin Low BIT 3 I/O3 B 0=Pin High 1=Pin Low BIT 2 I/O2 B 0=Pin High 1=Pin Low BIT 1 I/O1 B 0=Pin High 1=Pin Low BIT 0 I/O0 B 0=Pin High 1=Pin Low
2000 Feb 10
50
Philips Semiconductors
Objective specification
Dual UART
SC28L202
REGISTER MAPS
The registers of the SC28L202 are LOOSELY partitioned into two groups: those used in controlling data channels and those used in handling the actual data flow and status. Below is shown the general configuration of all the register addressed. The "Register Map Summary" shows the configuration of the lower four bits of the address that is the same for THE INDIVIDUAL UARTs. It also shows the addresses for the several in the address space of UART A and UART B that apply to the total chip configuration. The "Register Map Detail" shows the use of every address in the 8-bit address space.
REGISTER MAP DETAIL (based on 28L92)
Register Map NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a "" symbol Addressing Scheme: AB Default Extension +8 +16
NOTE: Addresses 0x00 to 0x0F represent the "C92 Register" map A(6:0) 000 0000 (0x00) 000 0001 (0x01) 000 0010 (0x02) 000 0011 (0x03) 000 0100 (0x04) 000 0101 (0x05) 000 0110 (0x06) 000 0111 (0x07) 000 1000 (0x08) 000 1001 (0x09) 000 1010 (0x0A) 000 1011 (0x0B) 000 1100 (0x0C) 000 1101 (0x0D) 000 1110 (0x0E) 000 1111 (0x0F) READ DEFAULT Mode Register (MR0 A, MR1 A, MR2 A) DEFAULT Status Register (SR A) Receiver FIFO Register (RxFIFO A) * Input Port Change Register (IPCR) DEFAULT * Interrupt Status Register (ISR) DEFAULT * Counter Timer Value Register Upper (CTVU 0) * Counter Timer Value Register Lower (CTVL 0) Mode Register (MR0 B, MR1 B, MR2 B) DEFAULT Status Register (SR B) Receiver FIFO Register (RxFIFO B) * Interrupt Vector Register (IVR) GLOBAL * Input Port Register (IPR) I/O(6:0) A * Start Counter Command DEFAULT C/T 0 * Stop Counter Command DEFAULT C/T 0 EXTENSION Receiver FIFO Fill Level (RxFL A) Transmitter FIFO Empty level (TxEL A) * Enhanced Operation Status (EOS) * Input Port Change Register Upper (IPCRU A) * Input Port Change Register Lower (IPCRL A) * Input Port Register (IPR A) * Counter Timer Value Register Upper (CTVU 0) * Counter Timer Value Register Lower (CTVL 0) Receiver FIFO Fill Level (RxFL B) Transmitter FIFO Empty level (TxEL B) * Input Port Change Register Upper (IPCRU B) * Input Port Change Register Lower (IPCRL B) * Input Port Register (IPR B) * Counter Timer Value Register Upper (CTVU 1) * Counter Timer Value Register Lower (CTVL 1) WRITE Mode Register (MR0 A, MR1 A, MR2 A) DEFAULT Clock Select Register (CSR A) DEFAULT Command Register (CR A) DEFAULT Transmitter FIFO Register (TxFIFO A) * Auxiliary Control Register (ACR) DEFAULT * Interrupt Mask Register (IMR) DEFAULT * Counter Timer Preset Register Upper (CTPU 0) * Counter Timer Preset Register Lower (CTPL 0) Mode Register (MR0 B, MR1 B, MR2 B) DEFAULT Clock Select Register (CSR B) DEFAULT Command Register (CR B) DEFAULT Transmitter FIFO Register (TxFIFO B) * Interrupt Vector Register (IVR) GLOBAL * Output Port Configuration Register (OPCR) I/O(7:2)B * Set Output Port Register (SOPR) I/O(7:0)B * Reset Output Port Register (ROPR) I/O(7:0)B
001 0000 (0x10) 001 0001 (0x11) 001 0010 (0x12) 001 0011 (0x13) 001 0100 (0x14) 001 0101 (0x15) 001 0110 (0x16) 001 0111 (0x17) 001 1000 (0x18) 001 1001 (0x19) 001 1010 (0x1A) 001 1011 (0x1B) 001 1100 (0x1C) 001 1101 (0x1D) 001 1110 (0x1E) 001 1111 (0x1F)
* Set Output Port Register (SOPR A) * Reset Output Port Register (ROPR A) Command Register Extension (CRx A) * I/O Port Configuration Register 0 (I/OPCR 0) * I/O Port Configuration Register 1 (I/OPCR 1) * Counter Timer Preset Register Upper (CTPU 0) * Counter Timer Preset Register Lower (CTPL 0) * Set Output Port Register (SOPR B) * Reset Output Port Register (ROPR B) Command Register Extension (CRx B) * I/O Port Configuration Register 2 (I/OPCR 2) * I/O Port Configuration Register 3 (I/OPCR 3) * Counter Timer Preset Register Upper (CTPU 1) * Counter Timer Preset Register Lower (CTPL 1)
2000 Feb 10
51
Philips Semiconductors
Objective specification
Dual UART
SC28L202
REGISTER MAP (BASED ON 28L92)
NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a "*" symbol A(6:0) 010 0000 (0x20) 010 0001 (0x21) 010 0010 (0x22) 010 0011 (0x23) 010 0100 (0x24) 010 0101 (0x25) 010 0110 (0x26) 010 0111 (0x27) 010 1000 (0x28) 010 1001 (0x29) 010 1010 (0x2A) 010 1011 (0x2B) 010 1100 (0x2C) 010 1101 (0x2D) 010 1110 (0x2E) 010 1111 (0x2F) 011 0000 (0x30) 011 0001 (0x31) 011 0010 (0x32) 011 0011 (0x33) 011 0100 (0x34) 011 0101 (0x35) 011 0110 (0x36) 011 0111 (0x37) 011 1000 (0x38) 011 1001 (0x39) 011 1010 (0x3A) 011 1011 (0x3B) 011 1100 (0x3C) 011 1101 (0x3D) 011 1110 (0x3E) 011 1111 (0x3F) READ EXTENSION Mode Register 0 (MR0 A) NEW ADDRESS Mode Register 1 (MR1 A) NEW ADDRESS Mode Register 2 (MR2 A) NEW ADDRESS Mode Register 3 (MR3 A) NEW ADDRESS * Counter/Timer Clock Source (CTCS 0) Interrupt Status Register (ISR A) * Programmable BRG Preset Lower (PBRGPL 0) * Programmable BRG Preset Upper (PBRGPU 0) Mode Register 0 (MR0 B) NEW ADDRESS Mode Register 1 (MR1 B) NEW ADDRESS Mode Register 2 (MR2 B) NEW ADDRESS Mode Register 3 (MR3 B) NEW ADDRESS * Counter/Timer Clock Source (CTCS 1) * Interrupt Status Register (ISR B) WRITE Mode Register 0 (MR0 A) NEW ADDRESS Mode Register 1 (MR1 A) NEW ADDRESS Mode Register 2 (MR2 A) NEW ADDRESS Mode Register 3 (MR3 A) NEW ADDRESS * Counter/Timer Clock Source (CTCS 0) * Interrupt Mask Register (IMR A) * Programmable BRG Preset Lower (PBRGPL 0) * Programmable BRG Preset Upper (PBRGPU 0) Mode Register 0 (MR0 B) NEW ADDRESS Mode Register 1 (MR1 B) NEW ADDRESS Mode Register 2 (MR2 B) NEW ADDRESS Mode Register 3 (MR3 B) NEW ADDRESS * Counter/Timer Clock Source (CTCS 1) * Interrupt Mask Register (IMR B)
Receiver Clock Select Register (RxCSR A) Transmitter Clock Select Register (TxCSR A) * Input Port Change Interrupt Enable (IPCE A) * Programmable BRG Clock Source (PBRGCS)
Receiver Clock Select Register (RxCSR A) Transmitter Clock Select Register (TxCSR A) * Input Port Change Interrupt Enable (IPCE A) * Programmable BRG Clock Source (PBRGCS)
* Programmable BRG Preset Lower (PBRGPL 1) * Programmable BRG Preset Upper (PBRGPU 1) Receiver Clock Select Register (RxCSR B) Transmitter Clock Select Register (TxCSR B) * Input Port Change Interrupt Enable (IPCE B)
* Programmable BRG Preset Lower (PBRGPL 1) * Programmable BRG Preset Upper (PBRGPU 1) Receiver Clock Select Register (RxCSR B) Transmitter Clock Select Register (TxCSR B) * Input Port Change Interrupt Enable (IPCE B)
2000 Feb 10
52
Philips Semiconductors
Objective specification
Dual UART
SC28L202
REGISTER MAP (BASED ON 28L92)
NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a "*" symbol A(6:0) 100 0000 (0x40) 100 0001 (0x41) 100 0010 (0x42) 100 0011 (0x43) 100 0100 (0x44) 100 0101 (0x45) 100 0110 (0x46) 100 0111 (0x47) 100 1000 (0x48) 100 1001 (0x49) 100 1010 (0x4A) 100 1011 (0x4B) 100 1100 (0x4C) 100 1101 (0x4D) 100 1110 (0x4E) 100 1111 (0x4F) READ NEW System Enable Status (SES A) Xon Character Register (XonCR A) Xoff Character Register (XoffCR A) Address Recognition Character (ARCR A) Xon/Xoff Interrupt Status Register (XISR A) Special Function Register (SFR A) Receiver FIFO Interrupt Level (RxFIL A) Transmitter FIFO Interrupt Level (TxFIL A) System Enable Status (SES B) Xon Character Register (XonCR B) Xoff Character Register (XoffCR B) Address Recognition Character (ARCR B) Xon/Xoff Interrupt Status Register (XISR B) Special Function Register (SFR B) Receiver FIFO Interrupt Level (RxFIL B) Transmitter FIFO Interrupt Level (TxFIL B) WRITE Watchdog, Character and X Enable(WCXER A) Xon Character Register (XonCR A) Xoff Character Register (XoffCR A) Address Recognition Character (ARCR A) Special Function Register (SFR A) Receiver FIFO Interrupt Level (RxFIL A) Transmitter FIFO Interrupt Level (TxFIL A) Watchdog, Character and X Enable (WCXER B) Xon Character Register (XonCR B) Xoff Character Register (XoffCR B) Address Recognition Character (ARCR B) Special Function Register (SFR B) Receiver FIFO Interrupt Level (RxFIL B) Transmitter FIFO Interrupt Level (TxFIL B)
101 0000 (0x50) 101 0001 (0x51) 101 0010 (0x52) 101 0011 (0x53) 101 0100 (0x54) 101 0101 (0x55) 101 0110 (0x56) 101 0111 (0x57) 101 1000 (0x58) 101 1001 (0x59) 101 1010 (0x5A) 101 1011 (0x5B) 101 1100 (0x5C) 101 1101 (0x5D) 101 1110 (0x5E) 101 1111 (0x5F)
Bidding Control Register - Break Change (BCRBRK A) Bidding Control Register - Change of State (BCRCOS A) Bidding Control Register - Counter/Timer (BCRCT A) Bidding Control Register - Xon (BCRx A) Bidding Control Register - Address (BCRA A) Bidding Control Register - Loop Back Error (BCRLBE A)
Bidding Control Register - Break Change (BCRBRK A) Bidding Control Register - Change of State (BCRCOS A) Bidding Control Register - Counter/Timer (BCRCT A) Bidding Control Register - Xon (BCRx A) Bidding Control Register - Address (BCRA A) Bidding Control Register - Loop Back Error (BCRLBE A)
Bidding Control Register - Break Change (BCRBRK B) Bidding Control Register - Change of State (BCRCOS B) Bidding Control Register - Counter/Timer (BCRCT B) Bidding Control Register - Xon (BCRx B) Bidding Control Register - Address (BCRA B) Bidding Control Register - Loop Back Error (BCRLBE B)
Bidding Control Register - Break Change (BCRBRK B) Bidding Control Register - Change of State (BCRCOS B) Bidding Control Register - Counter/Timer (BCRCT B) Bidding Control Register - Xon (BCRx B) Bidding Control Register - Address (BCRA B) Bidding Control Register - Loop Back Error (BCRLBE B)
2000 Feb 10
53
Philips Semiconductors
Objective specification
Dual UART
SC28L202
REGISTER MAP (BASED ON 28L92)
NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are denoted by a "*" symbol A(6:0) 110 0000 (0x60) 110 0001 (0x61) 110 0010 (0x62) 110 0011 (0x63) 110 0100 (0x64) 110 0101 (0x65) 110 0110 (0x66) 110 0111 (0x67) 110 1000 (0x68) 110 1001 (0x69) 110 1010 (0x6A) 110 1011 (0x6B) 110 1100 (0x6C) 110 1101 (0x6D) 110 1110 (0x6E) 110 1111 (0x6F) READ GLOBAL * Interrupt Control Register (ICR) * Current Interrupt Register (CIR) WRITE * Interrupt Control Register (ICR) * Update Current Interrupt Register (UCIR)
* Interrupt Vector Register (IVR) * Global Chip Configuration Register (GCCR) * Test & Revision Register (TRR)
* Interrupt Vector Register (IVR) * Global Chip Configuration Register (GCCR) * Test & Revision Register (TRR)
111 0000 (0x70) 111 0001 (0x71) 111 0010 (0x72) 111 0011 (0x73) 111 0100 (0x74) 111 0101 (0x75) 111 0110 (0x76) 111 0111 (0x77) 111 1000 (0x78) 111 1001 (0x79) 111 1010 (0x7A) 111 1011 (0x7B) 111 1100 (0x7C) 111 1101 (0x7D) 111 1110 (0x7E) 111 1111 (0x7F)
* Global Interrupt Channel Register (GICR) * Global Interrupt Byte Count Register (GIBCR) *Global Interrupt Type Register (GITR) * Global RxFIFO Register (GRxFIFO)
* Global TxFIFO Register (GTxFIFO)
* Scan Test Control Register (STCR)
* Scan Test Control Register (STCR)
2000 Feb 10
54
Philips Semiconductors
Objective specification
Dual UART
SC28L202
ABSOLUTE MAXIMUM RATINGS1
SYMBOL Tamb Tstg VCC VSS P P PARAMETER Operating ambient temperature range2 Storage temperature range Voltage from VCC to GND3 -0.5 to +7.0 Voltage from any pin to GND3 Power dissipation (PLCC44) Power dissipation (PQFP44) Derating factor above 25 _C (PLCC44) Derating factor above 25 _C (PQFP44) RATING Note4 -65 to +150 -0.5 to +7.0 -0.5 to VCC +0.5 2.4 1.78 19 15 UNIT _C _C V V W W mw/_C Mw/_C
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on + 150_C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature range.
2000 Feb 10
55
Philips Semiconductors
Objective specification
Dual UART
SC28L202
DC ELECTRICAL CHARACTERISTICS123 (NOMINAL 5 VOLTS)
Vcc = 5v 10% Ta = - 40 to +85 _C unless otherwise specified SYMBOL VIL VIH VIH VOL VOH IIX1PD IILX1 IIHX1 Ii IOZH IOZL IODL IODH ICC PARAMETER Input low voltage VIH Input high voltage (except X1/CLK) Input high voltage (X1/CLK) Output low voltage Output high voltage (except OD outputs)4 X1/CLK input current - power down X1/CLK input low current - operating X1/CLK input high current - operating Input leakage current: exce t in ut ort ins In ut ort ins All except input port pins Input port pins5 Output off current high, 3-State data bus Output off current low, 3-State data bus Open-drain output low current in off-state Open-drain output high current in off-state Power supply current:6 Operating mode Power down mode7 TEST CONDITIONS -40 to +85_C IOL = 4 ma IOH = -400 ua VIN = 0 to VCC VIN = 0 VIN = VCC VIN = 0 to VCC VIN = 0 to VCC VIN = VCC VIN = 0V VIN = 0 VIN = VCC CMOS input levels CMOS input levels LIMITS Min 2.4 0.8*Vcc Vcc - 0.5 0.5 -130 0 -0.5 -8 -0.5 -0.5 0.5 25 1 UNIT Typ 1.2 1.5 2.4 0.2 0.05 Max 0.8 V V V V v A A A A A A A A A ma a
0.4 0.5 0 130 +0.5 +0.5 0.5
0.05 0.05
5
NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V, as appropriate. 3. Typical values are at +25_C, typical supply voltages, and typical processing parameters. 4. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7K ohm to VCC. 5. Input port pins have active pull up transistors that will source a typical 2 A from Vcc when the input pins are at Vss. Input port pins at VCC source 0.0 A 6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC -0.2V and VSS + 0.2V. 7. See UART application note for power down currents of 10 ua or less.
2000 Feb 10
56
Philips Semiconductors
Objective specification
Dual UART
SC28L202
AC CHARACTERISTICS1,2,3 (NOMINAL 5 VOLTS)
Vcc = 5v 10% Ta = - 40 to +85 _C unless otherwise specified Symbol Parameter Reset timing (See Figure 3) tRES Reset Pulse Width Bus Timing5 (See Figure ___) t*AS A6-A0 setup time to RDN, WRN Low t*AH A6-A0 hold time from RDN, WRN low t*CS CEN setup time to RDN, WRN low t*CH CEN Hold time from RDN. WRN Hi t*RW WRN, RDN pulse width (Low time) t*DD Data valid after RDN low (125 pf load) See loading table for smaller loads t*DA RDN low to data bus active6 t*DF Data bus floating after RDN or CEN high t*DI RDN or CEN high to data bus invalid7 t*DS Data bus setup time before WRN or CEN high (write cycle) t*DH Data hold time after WRN high t*RWD High time between read and/or write cycles5,7 Port Timing5 (See Figure 7) t*PS Port in setup time before RDN low (Read IP ports cycle) t*PH Port in hold time after RDN high t*PD OP port valid after WRN or CEN high (OPR write cycle) Interrupt Timing (See Figure 8) INTRN (or I/O(7:3)B when used as interrupts) negated from: Read RxFIFO (RxRDY/FFULL interrupt) Write TxFIFO (TxRDY interrupt) t*IR Reset Command (delta break change interrupt) Stop C/T command (Counter/timer interrupt Read IPCR (delta input port change interrupt) Write IMR (Clear of change interrupt mask bit(s)) Clock Timing (See Figure 9) t*CLK X1/CLK high or low time f*CLK X1/CLK frequency (7.0 to 16.2 MHz with crystal) f*CTC C/T Clk (IP2) high or low time (C/T external clock input) f*CTC C/T Clk (IP2) frequency8 t*RX RxC high or low time (16X) f*RX RxC Frequency (16X) RxC Frequency (1x)8,9 t*TX TxC High or low time (16X) f*TX TxC frequency (16X) TxC frequency (1X)8,9 Transmitter Timing (See Figure 12) t*TXD TxD output delay from TxC low (TxC input pin) t*TCS Output delay from TxC output pin low to TxD data output Receiver Timing (See Figure 13) t*RXS RxD data setup time to RxC high t*RXH RxD data hold time from RxC high 68000 or Motorola bus timing (See Figure ___) tDCR DACKN Low (read cycle) from X1 High TDCW DACKN Low (write cycle) from X1 High TDAH DACKN High from CSN or IACKN high tDAT DACKN High impedance from CSN or IACKN high tCSC CSN or IACKN setup time to X1 high for minimum DACKN cycle LIMITS4 Min Typ 100 10 20 0 0 15 0 20 0 25 0 15 0 0 17 -15 12 -20 -20 40 18 6 Max UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
11 15
40
60
40 40 40 40 40 40 30 1.0 30 0 30 0 0 30 0 40 6 50 50 40 40 15 15 8 8 8 20 14.7 20
60 60 60 60 60 60
ns ns ns ns ns ns ns MHz ns MHz ns MHz MHz ns MHz MHz ns ns ns ns
50
50 3 50 3 60 30
20 20 10 10
10
ns ns ns ns ns
2000 Feb 10
57
Philips Semiconductors
Objective specification
Dual UART
SC28L202
NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V, as appropriate. 3. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7K ohm to VCC. 4. Typical values are at +25_C, typical supply voltages, and typical processing parameters. 5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the `strobing' input. CEN and RDN (also CEN and WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. Guaranteed by characterization of sample units. 7. If CEN is used as the `strobing' input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must be negated for t RWD time to guarantee that any status register changes are valid. 8. Minimum frequencies are not tested but are guaranteed by design. 9. Clocks for 1X mode should be symmetrical.
2000 Feb 10
58
Philips Semiconductors
Objective specification
Dual UART
SC28L202
DC ELECTRICAL CHARACTERISTICS1,2,3 (NOMINAL 3.3 VOLTS)
Vcc = 3.3v 10% Ta = - 40 to +85 _C unless otherwise specified SYMBOL VIL VIH VOL VOH IIX1PD IILX1 IIHX1 Ii PARAMETER Input low voltage Input high voltage (X1/CLK) Output low voltage Output high voltage (except OD outputs)4 X1/CLK input current - power down X1/CLK input low current - operating X1/CLK input high current - operating Input leakage current: All except input port pins Input port pins5 TEST CONDITIONS LIMITS Min 0.8*Vcc IOL = 4 ma IOH = -400 ua VIN = 0 to VCC VIN = 0 VIN = VCC Vcc-0.5 -0.5 -80 0 UNIT Typ 0.65 1.7 0.2 Vcc-0.2 0.05 Max 0.2*Vcc 0.4 +0.5 0 80 V V V v A A A
IOZH IOZL IODL IODH ICC
Output off current high, 3-State data bus Output off current low, 3-State data bus Open-drain output low current in off-state Open-drain output high current in off-state Power supply current:6 Operating mode Power down mode7
VIN = 0 to VCC VIN = 0 to VCC VIN = VCC VIN = 0V VIN = 0 VIN = VCC CMOS input levels CMOS input levels
-0.5 -8 -0.5 -0.5
0.05 0.5
+0.5 +0.5 0.5
0.5 25 1
A A A A A A ma A
5.0
NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V, as appropriate. 3. Typical values are at +25_C, typical supply voltages, and typical processing parameters. 4. Test conditions for outputs: C L = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: C L = 50 pF, R L = 2.7K ohm to VCC. 5. Input port pins have active pull up transistors that will source a typical 2 A from Vcc when the input pins are at Vss. Input port pins at Vcc source 0.0 A 6. All outputs are disconnected. Inputs are switching between CMOS levels of VCC -0.2V and VSS + 0.2V. 7. See UART application note for power down currents of 10 ua or less.
2000 Feb 10
59
Philips Semiconductors
Objective specification
Dual UART
SC28L202
AC CHARACTERISTICS1,2,3 (NOMINAL 3.3 VOLTS)
Vcc = 3.3v 10% Ta = - 40 to +85 _C unless otherwise specified Symbol Parameter Reset timing (See Figure 3) tRES Reset Pulse Width Bus Timing (See Figure ___) t*AS A6-A0 setup time to RDN, WRN Low t*AH A6-A0 hold time from RDN, WRN low t*CS CEN setup time to RDN, WRN low t*CH CEN Hold time from RDN. WRN Hi t*RW WRN, RDN pulse width (Low time) t*DD Data valid after RDN low (125 pf load) See load table for smaller loads t*DA RDN low to data bus active t*DF Data bus floating after RDN or CEN high t*DI RDN or CEN high to data bus invalid t*DS Data bus setup time before WRN or CEN high (write cycle) t*DH Data hold time after WRN high t*RWD High time between read and/or write cycles Port Timing (See Figure 7) t*PS Port in setup time before RDN low (Read IP ports cycle) t*PH Port in hold time after RDN high t*PD OP port valid after WRN or CEN high (OPR write cycle) Interrupt Timing (See Figure 8) INTRN (or I/O(7:3)B when used as interrupts) negated from: Read RxFIFO (RxRDY/FFULL interrupt) Write TxFIFO (TxRDY interrupt) t*IR Reset Command (delta break change interrupt) Stop C/T command (Counter/timer interrupt Read IPCR (delta input port change interrupt) Write IMR (Clear of change interrupt mask bit(s)) Clock Timing (See Figure 9) t*CLK X1/CLK high or low time f*CLK X1/CLK frequency (7.0 to 16.2 MHz with crystal) f*CTC C/T Clk (IP2) high or low time (C/T external clock input) f*CTC C/T Clk (IP2) frequency t*RX RxC high or low time (16X) f*RX RxC Frequency (16X) RxC Frequency (1x) t*TX TxC High or low time (16X) f*TX TxC frequency (16X) TxC frequency (1X) Transmitter Timing (See Figure 12) t*TXD TxD output delay from TxC low (TxC input pin) t*TCS Output delay from TxC output pin low to TxD data output Receiver Timing (See Figure 13) t*RXS RxD data setup time to RxC high t*RXH RxD data hold time from RxC high 68000 or Motorola bus timing (See Figure ___) tDCR DACKN Low (read cycle) from X1 High TDCW DACKN Low (write cycle) from X1 High TDAH DACKN High from CSN or IACKN high tDAT DACKN High impedance from CSN or IACKN high tCSC CSN or IACKN setup time to X1 high for minimum DACKN cycle LIMITS4 Min 100 10 25 0 0 20 0 15 0 25 0 20 0 0 20 -15 14 -20 -20 50 25 Typ 18 6 15 Max UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15 20
50
70
40 40 40 40 40 40 30 1 30 0 30 0 0 30 0 40 6 50 50 40 40 18 18 2 10 10 20 14.7 20
60 60 60 60 60 60
ns ns ns ns ns ns ns MHz ns MHz ns MHz MHz ns MHz MHz ns ns ns ns
34 8 24 1 24 1 60 30
25 25 5 15
ns ns ns ns
15
2000 Feb 10
60
Philips Semiconductors
Objective specification
Dual UART
SC28L202
NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5 ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V, as appropriate. 3. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50 pF, RL = 2.7K ohm to VCC. 4. Typical values are at +25_C, typical supply voltages, and typical processing parameters. 5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the `strobing' input. CEN and RDN (also CEN and WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. Guaranteed by characterization of sample units. 7. If CEN is used as the `strobing' input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must be negated for t RWD time to guarantee that any status register changes are valid. 8. Minimum frequencies are not tested but are guaranteed by design. 9. Clocks for 1X mode should be symmetrical.
RESETN
tRES
SD00133
Figure 1. Reset Timing (80XXX mode)
A0-A3
tAS tAH CEN tCS tRW RDN tCH tRWD
tDD D0-D7 (READ) NOT VALID
tDF
FLOAT
VALID
FLOAT
tRWD WDN
tDS tDH D0-D7 (WRITE) VALID
SD00087
Figure 2. Bus Timing (80XXX mode)
RESETN
tRES
SD00109
Figure 3. Reset Timing (68XXX mode)
2000 Feb 10
61
Philips Semiconductors
Objective specification
Dual UART
SC28L202
tCSC X1/CLK tAS A1-A4 tCS RWN CSN tAH tDD D0-D7 tDA DTACKN tDCR tDAH tDAT NOT VALID DATA VALID tRWD tCH
tDF
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
SD00687
Figure 4. Bus Timing (Read Cycle) (68XXX mode)
tCSC X1/CLK tAS A1-A4 tCS tCH
RWN
CSN
tAH
tRWD
D0-D7 tDS DTACKN tDCW tDAT NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. tDAH tDH
SD00688
Figure 5. Bus Timing (Write Cycle) (68XXX mode)
2000 Feb 10
62
Philips Semiconductors
Objective specification
Dual UART
SC28L202
tCSC X1/CLK
INTRN
IACKN
tDD D0-D7 tCSD tDAL DTACKN tDCR NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. tDAH tDAT
tDF
SD00149
Figure 6. Interrupt Cycle Timing (68XXX mode)
RDN
tPS
tPH
IP0-IP6
(a) INPUT PINS
WRN
tPD
OP0-OP7
OLD DATA
NEW DATA
(b) OUTPUT PINS
SD00135
Figure 7. Port Timing
2000 Feb 10
63
Philips Semiconductors
Objective specification
Dual UART
SC28L202
WRN
VM
tIR INTERRUPT 1 OUTPUT VOL +0.5V VOL
RDN
VM
tIR INTERRUPT 1 OUTPUT VOL +0.5V VOL NOTES: 1. INTRN or OP3-OP7 when used as interrupt outputs. 2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. SD00136
Figure 8. Interrupt Timing (80xxx mode)
tCLK tCTC tRx tTx X1/CLK CTCLK RxC TxC tCLK tCTC tRx tTx
VCC NOTE: RESISTOR REQUIRED FOR TTL INPUT. CLK
470
X1
*NOTE: X2 MUST BE LEFT OPEN.
X2*
3pF PARASITIC CAPACITANCE
SC28L92 X1 2pF
C1 50k to 100k C2
X2 3pF PARASITIC CAPACITANCE 14.7456MHz
4pF
TO UART CIRCUIT
C1 = C2 24pF FOR CL = 20pF C1 and C2 should be chosen according to the crystal manufacturer's specification. C1 and C2 values will include any parasitic capacitance of the wiring and X1 X2 pins. Package capacitance approximately 4pF.
SD00689
Figure 9. Clock Timing
2000 Feb 10
64
Philips Semiconductors
Objective specification
Dual UART
SC28L202
1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT)
tTXD
TxD
tTCS
TxC (1X OUTPUT)
SD00138
Figure 10. Transmitter External Clocks
RxC (1X INPUT)
tRXS
tRXH
RxD
SD00139
Figure 11. Receiver External Clock
TxD TRANSMITTER ENABLED TxRDY (SR2)
D1
D2
D3
BREAK
D4
D6
WRN D1 CTSN1 (IP0) D8 D9 START BREAK D10 STOP BREAK D11 WILL NOT BE WRITTEN TO THE TxFIFO D12
RTSN2 (OP0) OPR(0) = 1 NOTES: 1. Timing shown for MR2(4) = 1. 2. Timing shown for MR2(5) = 1. OPR(0) = 1
SD00155
Figure 12. Transmitter Timing
2000 Feb 10
65
Philips Semiconductors
Objective specification
Dual UART
SC28L202
RxD
D1
D2
D8
D9
D10
D11
D12
D13
RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL (OP5)2 RDN STATUS DATA D1 OVERRUN (SR4) RTS1 (OP0) OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1. 2. Shown for OPCR(4) = 1 and MR(6) = 0. D11 WILL BE LOST DUE TO OVERRUN
D12, D13 WILL BE LOST DUE TO RECEIVER DISABLE.
STATUS DATA STATUS DATA STATUS DATA D2 D3 D10 RESET BY COMMAND
SD00156
Figure 13. Receiver Timing
MASTER STATION TxD
BIT 9 ADD#1 1 D0
BIT 9 0
BIT 9 ADD#2 1
TRANSMITTER ENABLED TxRDY (SR2)
WRN MR1(4-3) = 11 MR1(2) = 1 ADD#1 MR1(2) = 0 D0 MR1(2) = 1 ADD#2
PERIPHERAL STATION BIT 9 RxD RECEIVER ENABLED RxRDY (SR0) RDN/WRN MR1(4-3) = 11 0
BIT 9 ADD#1 1 D0
BIT 9 0
BIT 9 ADD#2 1
BIT 9 0
ADD#1
STATUS DATA D0
STATUS DATA ADD#2
SD00096
Figure 14. Wake-Up Mode
2000 Feb 10
66
Philips Semiconductors
Objective specification
Dual UART
SC28L202
I = 2.4mA INTRN DACKN 125pF I = 2.4mA VOL return to VCC for a 0 level I = 400A VOH return to VSS for a 1 level +5V
D0-D7 TxDA/B OP0-OP7 125pF
SD00690
Figure 15. Test Conditions on Outputs
2000 Feb 10
67
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
2000 Feb 10
68
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
2000 Feb 10
69
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
NOTES
2000 Feb 10
70
Philips Semiconductors
Objective specification
Dual universal asynchronous receiver/transmitter (DUART)
SC28L202
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 02-00 Document order number: 9397 750 06826
Philips Semiconductors
2000 Feb 10 71

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